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authorKarel Kočí <cynerd@email.cz>2015-03-22 14:05:00 +0100
committerKarel Kočí <cynerd@email.cz>2015-03-22 14:05:00 +0100
commita5bb06281011f4f0edd6f7b9331f149bd256d495 (patch)
tree7b576d3b3a737e94a601a236523612369152f52b /src/spi.c
parent9447247c1ab0b0a02c5ec87c138135953986975c (diff)
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SPI moved from src subfolder and mode changes
SPI USI should now work. SPI USI is now documented. Removing architecture specific folders in src.
Diffstat (limited to 'src/spi.c')
-rw-r--r--src/spi.c47
1 files changed, 47 insertions, 0 deletions
diff --git a/src/spi.c b/src/spi.c
new file mode 100644
index 0000000..8462905
--- /dev/null
+++ b/src/spi.c
@@ -0,0 +1,47 @@
+#include "../spi.h"
+#include "mcu/mcu.h"
+
+inline void ioe_spi_join(void) {
+ // TODO
+}
+
+inline int ioe_spi_bussy(void) {
+}
+
+#ifdef IOE_SPI_MASTER
+inline void ioe_spi_init(void) {
+ // Set MOSI and SCK output
+ DDR_SPI |= _BV(DD_MOSI) | _BV(DD_SCLK);
+ // Set MISO pull up resistor
+ PORT_SPI |= _BV(PORT_MISO);
+ // Enable SPI interrupt
+ SPCR |= _BV(SPIE);
+ // Enable SPI master and set clock rate fck/16
+ SPCR = _BV(SPE) | _BV(MSTR) | _BV(SPR0);
+}
+
+inline void ioe_spi_transfer(int8_t data) {
+ SPDR = data;
+}
+
+#else /* IOE_SPI_MASTER */
+inline void ioe_spi_init(void) {
+ // Set MISO as output
+ DDR_SPI = _BV(DD_MISO);
+ // Set SCLK and MOSI pull up resistor
+ PORT_SPI |= _BV(PORT_SCLK) | _BV(PORT_MOSI);
+ // Enable SPI interrupt
+ SPCR |= _BV(SPIE);
+ // Enable SPI
+ SPCR = _BV(SPE);
+}
+
+inline void ioe_spi_expose(int8_t data) {
+ SPDR = data;
+}
+
+#endif /* IOE_SPI_MASTER */
+
+SIGNAL(SPI_STC_vect) {
+ ioe_spi_retrieve(SPDR);
+}