aboutsummaryrefslogtreecommitdiff
path: root/qtmips_machine/cache.h
blob: 1882c6c4f9c107d78c6d0dfdcac9ec55758e47ae (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
#ifndef CACHE_H
#define CACHE_H

#include <memory.h>
#include <machineconfig.h>
#include <stdint.h>
#include <time.h>

namespace machine {

class Cache : public MemoryAccess {
    Q_OBJECT
public:
    Cache(Memory *m, const MachineConfigCache *c);

    void wword(std::uint32_t address, std::uint32_t value);
    std::uint32_t rword(std::uint32_t address) const;

    void flush(); // flush cache
    void sync(); // Same as flush

    unsigned hit() const; // Number of recorded hits
    unsigned miss() const; // Number of recorded misses

    void reset(); // Reset whole state of cache

    const MachineConfigCache &config() const;
    // TODO getters for cells

private:
    MachineConfigCache cnf;
    Memory *mem;

    struct cache_data {
        bool valid, dirty;
        std::uint32_t tag;
        std::uint32_t *data;
    };
    mutable struct cache_data **dt;

    union {
        time_t ** lru; // Access time
        unsigned **lfu; // Access count
    } replc; // Data used for replacement policy

    mutable unsigned hitc, missc; // Hit and miss counters

    void access(std::uint32_t address, std::uint32_t **data, bool read) const;
    void kick(unsigned associat_indx, unsigned row) const;
    std::uint32_t base_address(std::uint32_t tag, unsigned row) const;
};

}

#endif // CACHE_H