| Commit message (Expand) | Author | Age |
|---|
| ... | |
| * | Rewrite instruction decoding to be generic and mostly architecture independent. | Pavel Pisa | 2019-02-05 |
| * | Setup initial PC according executable entry form ELF file if it is non zero. | Pavel Pisa | 2019-02-04 |
| * | Define uncached region in range from 0xf0000000 to 0xffffffff. | Pavel Pisa | 2019-02-04 |
| * | Remove almost all direct access to opcode and function from the core. | Pavel Pisa | 2019-02-04 |
| * | Take into account actual requirements for rs, rt and rd write for individual ... | Pavel Pisa | 2019-02-04 |
| * | Unified instructions table and access type move to machinedefs.h . | Pavel Pisa | 2019-02-04 |
| * | Include more complex insert-sort test which checks memory and cache. | Pavel Pisa | 2019-02-04 |
| * | Primitive implementation of cache instruction. | Pavel Pisa | 2019-02-04 |
| * | Simplify core test by use of common function to run test machine. | Pavel Pisa | 2019-02-04 |
| * | Add license to the source files. | Pavel Pisa | 2019-02-04 |
| * | Correct write-back cache behavior. | Pavel Pisa | 2019-02-04 |
| * | Correct memory view updates for uncached and write-through case. | Pavel Pisa | 2019-02-03 |
| * | Implement BREAK instruction to stop continuous execution. | Pavel Pisa | 2019-02-03 |
| * | Implement instructions MULT, MULTU, DIV, DIVU. | Pavel Pisa | 2019-02-03 |
| * | Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ inst... | Pavel Pisa | 2019-02-02 |
| * | Include test for jump and link processing. | Pavel Pisa | 2019-02-02 |
| * | Add test for forwarding in ALU operations. | Pavel Pisa | 2019-02-02 |
| * | Correct ALU test for SUB exception. | Pavel Pisa | 2019-02-02 |
| * | Include support for JALR support. | Pavel Pisa | 2019-01-31 |
| * | Initial support for JAL. | Pavel Pisa | 2019-01-31 |
| * | Correct signed arithmetic overflow exception. | Pavel Pisa | 2019-01-31 |
| * | Display rs, rt, rd and write register number in all stages. | Pavel Pisa | 2019-01-31 |
| * | Correct processing of ORI, ANDI, XORI instructions which require zero-extende... | Pavel Pisa | 2019-01-31 |
| * | Do not replace rt by forward if instruction in T_R or store. | Pavel Pisa | 2019-01-30 |
| * | Display execution stage forward signals in the view. | Pavel Pisa | 2019-01-30 |
| * | Correct hazards processing. | Pavel Pisa | 2019-01-30 |
| * | Add few more labels | Karel Kočí | 2018-05-24 |
| * | Add buses statis views | Karel Kočí | 2018-05-24 |
| * | Add cache view renderer | Karel Kočí | 2018-05-23 |
| * | Add cache statistics | Karel Kočí | 2018-05-23 |
| * | Fix load and store instructions | Karel Kočí | 2018-05-02 |
| * | Initial implementation of cache view | Karel Kočí | 2018-04-17 |
| * | Change presets | Karel Kočí | 2018-04-15 |
| * | Show cache statistics in Memory block in coreview | Karel Kočí | 2018-04-15 |
| * | Drop quick jump buttons from memory view | Karel Kočí | 2018-04-10 |
| * | Fix some instruction string representation | Karel Kočí | 2018-04-08 |
| * | Change string format for some instruction | Karel Kočí | 2018-04-08 |
| * | Implement LUI | Karel Kočí | 2018-04-08 |
| * | Implement sync for memory | Karel Kočí | 2018-04-08 |
| * | Ensure that set, block and assoc. is in minimum one | Karel Kočí | 2018-04-08 |
| * | Integrate cache with rest of the machine core | Karel Kočí | 2018-04-08 |
| * | Add associative cache | Karel Kočí | 2018-04-08 |
| * | Drop unneeded mask in memory implementation | Karel Kočí | 2018-04-07 |
| * | Add initial implementatio of caches | Karel Kočí | 2018-04-07 |
| * | Just note that we are checking endianity automatically | Karel Kočí | 2018-04-05 |
| * | Use whole words in memory | Karel Kočí | 2018-04-05 |
| * | Fix forwarding checker for I and J and S* instructions | Karel Kočí | 2018-03-06 |
| * | Implement Cache configuration | Karel Kočí | 2018-03-06 |
| * | Forward from execute stage to decode stage latch | Karel Kočí | 2018-02-14 |
| * | Do empty fetch stage to report fetch even if we stall | Karel Kočí | 2018-02-14 |
