| Commit message (Collapse) | Author | Age | ||
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| * | Setup initial PC according executable entry form ELF file if it is non zero. | Pavel Pisa | 2019-02-04 | |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Define uncached region in range from 0xf0000000 to 0xffffffff. | Pavel Pisa | 2019-02-04 | |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Remove almost all direct access to opcode and function from the core. | Pavel Pisa | 2019-02-04 | |
| | | | | | | | | Remaining are MOVZ and MOVN in the execution phase and all branch and jump operations in handle_pc(). Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Take into account actual requirements for rs, rt and rd write for individual ↵ | Pavel Pisa | 2019-02-04 | |
| | | | | | | | instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Unified instructions table and access type move to machinedefs.h . | Pavel Pisa | 2019-02-04 | |
| | | | | | | | | This allows to specify requirement for RS and RD on instruction basis even for T_R / ALU instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Include more complex insert-sort test which checks memory and cache. | Pavel Pisa | 2019-02-04 | |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Primitive implementation of cache instruction. | Pavel Pisa | 2019-02-04 | |
| | | | | | | | | When any variant of cache instruction is detected flush and invalidate whole data cache. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Simplify core test by use of common function to run test machine. | Pavel Pisa | 2019-02-04 | |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Add license to the source files. | Pavel Pisa | 2019-02-04 | |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Correct write-back cache behavior. | Pavel Pisa | 2019-02-04 | |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Correct memory view updates for uncached and write-through case. | Pavel Pisa | 2019-02-03 | |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Implement BREAK instruction to stop continuous execution. | Pavel Pisa | 2019-02-03 | |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Implement instructions MULT, MULTU, DIV, DIVU. | Pavel Pisa | 2019-02-03 | |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ ↵ | Pavel Pisa | 2019-02-02 | |
| | | | | | | | | | | | | instructions. The previous code worked by chance only because decode has been fully processed including forwarding from M and W before PC processing started. But in real hardware the PC processing runs in parallel with ALU and cannot read its results in the same cycle. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Include test for jump and link processing. | Pavel Pisa | 2019-02-02 | |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Add test for forwarding in ALU operations. | Pavel Pisa | 2019-02-02 | |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Correct ALU test for SUB exception. | Pavel Pisa | 2019-02-02 | |
| | | | | | | | | | | | | | The operation 3 - 4 = 1 is legal integer arithmetic operation. Changed to 0x80000003 - 4 = 0x7fffffff 2147483651 - 4 = 2147483647 which overflows. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Include support for JALR support. | Pavel Pisa | 2019-01-31 | |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Initial support for JAL. | Pavel Pisa | 2019-01-31 | |
| | | | | | | | | The JR, BEQ, BNE are most probably incorrect still. There is missing forwarding for pipelined execution. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Correct signed arithmetic overflow exception. | Pavel Pisa | 2019-01-31 | |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Display rs, rt, rd and write register number in all stages. | Pavel Pisa | 2019-01-31 | |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Correct processing of ORI, ANDI, XORI instructions which require ↵ | Pavel Pisa | 2019-01-31 | |
| | | | | | | | zero-extended immediate. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Do not replace rt by forward if instruction in T_R or store. | Pavel Pisa | 2019-01-30 | |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Display execution stage forward signals in the view. | Pavel Pisa | 2019-01-30 | |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Correct hazards processing. | Pavel Pisa | 2019-01-30 | |
| | | | | | | | | | The shorter loop has priority. This is achieved by later processing when it replaces possible result from longer loop over W stage. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | |||
| * | Add few more labels | Karel Kočí | 2018-05-24 | |
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| * | Add buses statis views | Karel Kočí | 2018-05-24 | |
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| * | Add cache view renderer | Karel Kočí | 2018-05-23 | |
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| * | Add cache statistics | Karel Kočí | 2018-05-23 | |
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| * | Fix load and store instructions | Karel Kočí | 2018-05-02 | |
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| * | Initial implementation of cache view | Karel Kočí | 2018-04-17 | |
| | | | | | It needs some more work to look nice but it already works. | |||
| * | Change presets | Karel Kočí | 2018-04-15 | |
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| * | Show cache statistics in Memory block in coreview | Karel Kočí | 2018-04-15 | |
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| * | Drop quick jump buttons from memory view | Karel Kočí | 2018-04-10 | |
| | | | | | | They are not implemented and even if they would they usage would be little bit funky as they would jump by internal amount of page memory. | |||
| * | Fix some instruction string representation | Karel Kočí | 2018-04-08 | |
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| * | Change string format for some instruction | Karel Kočí | 2018-04-08 | |
| | | | | | This makes our string format closer to original assembler. | |||
| * | Implement LUI | Karel Kočí | 2018-04-08 | |
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| * | Implement sync for memory | Karel Kočí | 2018-04-08 | |
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| * | Ensure that set, block and assoc. is in minimum one | Karel Kočí | 2018-04-08 | |
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| * | Integrate cache with rest of the machine core | Karel Kočí | 2018-04-08 | |
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| * | Add associative cache | Karel Kočí | 2018-04-08 | |
| | | | | | Not fully tested yet. | |||
| * | Drop unneeded mask in memory implementation | Karel Kočí | 2018-04-07 | |
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| * | Add initial implementatio of caches | Karel Kočí | 2018-04-07 | |
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| * | Just note that we are checking endianity automatically | Karel Kočí | 2018-04-05 | |
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| * | Use whole words in memory | Karel Kočí | 2018-04-05 | |
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| * | Fix forwarding checker for I and J and S* instructions | Karel Kočí | 2018-03-06 | |
| | | | | | THere are exceptions when we care about forwarding and when we don't. | |||
| * | Implement Cache configuration | Karel Kočí | 2018-03-06 | |
| | | | | | This commit implements both cache configuration for machine and for gui. | |||
| * | Forward from execute stage to decode stage latch | Karel Kočí | 2018-02-14 | |
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| * | Do empty fetch stage to report fetch even if we stall | Karel Kočí | 2018-02-14 | |
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| * | Another swap in instruction decoding | Karel Kočí | 2018-02-14 | |
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index : qtmips | |
| MIPS CPU emulator for education purposes | Gitolite user |
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path: root/qtmips_machine