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* Implement ROTR and ROTRV and full decode of WSBH, SEB and SEH.Pavel Pisa2019-02-24
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add some more labels and clarify rs, rt, rd in execute stage.Pavel Pisa2019-02-24
| | | | | | | This allows simple visual compare of rs and rt in execution stage with register number to be written in memory and write-back stages. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add support for goto to selected symbol address.Pavel Pisa2019-02-22
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Ensure that cache view and memory status are updated after cache flush.Pavel Pisa2019-02-21
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Added test for LWR, LWL, SWR and SWL instructions.Pavel Pisa2019-02-21
| | | | | | | The reference data has been obtained by running application under userspace MIPS QEMU. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add burst time and store timing in the config.Pavel Pisa2019-02-21
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Distinguish between write-through cache with allocate and update only if hit.Pavel Pisa2019-02-20
| | | | | | | Add into cache statistic number of backing/main memory accesses. Correction of meaning and computation of the cache statistic. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Update project files to adapt for release and debug libraries location for ↵Pavel Pisa2019-02-19
| | | | | | Windows builds. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Clear LFU statistic for the kicked out cache-line.Pavel Pisa2019-02-18
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Report forward and stall for branches and add forward to execution phase.Pavel Pisa2019-02-18
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct ADD operation to map to ALU variant with overflow checking.Pavel Pisa2019-02-18
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Visualize request to stall and stall in execution phase and exception sources.Pavel Pisa2019-02-18
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Stall the pipeline even for branch which requires memory read as argument.Pavel Pisa2019-02-18
| | | | | | | | | | This type of the hazard doe not cause problems in the simulator because processing of memory stage is already finished at time when PC handling is started but it would cause problems in real hardware where PC handling is processed in parallel to memory load. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Do not update instruction in the decode stage when stalled.Pavel Pisa2019-02-17
| | | | | | | Decode dt_d represents next input to execute stage not state of decode stage at this moment. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Ignore LWC1, LWD1, SWC1 and SDC1 instructions.Pavel Pisa2019-02-17
| | | | | | This allows to use MUSL Lib C printf and scanf implementations. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Pass arithmetic exception trough pipeline and implement trap support and ↵Pavel Pisa2019-02-17
| | | | | | instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Change RGB LEDs signals and slots to unsigned value.Pavel Pisa2019-02-16
| | | | | | | Signed value caused in the conversion incorrect behavior for some corner cases. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Multiply and accumulate and CLZ/CLO operations added.Pavel Pisa2019-02-15
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement EXT instruction used in GLIBC startup.Pavel Pisa2019-02-15
| | | | | | It requires one more field to pass to ALU. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Core: move complex memory operation to own function and implement LWL, LWR, ↵Pavel Pisa2019-02-15
| | | | | | | | SWL, SWR. The move makes basic memory stage processing more readable. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Fill the rest of ALU opcode table to file all 64 entries.Pavel Pisa2019-02-14
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct program loader to open ELF file in binary mode on Windows.Pavel Pisa2019-02-14
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Ignore PREF instruction.Pavel Pisa2019-02-14
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented graphic representation and update of line and RGB LEDs.Pavel Pisa2019-02-14
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement function to setup core C0 userlocal register.Pavel Pisa2019-02-14
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement MUL operation which stores result to the register.Pavel Pisa2019-02-14
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Ensure that single step does not run chunk of instructions instead of one.Pavel Pisa2019-02-13
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented three dials equivalent to MZ_APO RGB dials.Pavel Pisa2019-02-13
| | | | | | | Tested with code compiled by Linux PIC based GCC compiler with calling musl-libc sprintf function. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Initialize SP to safe RAM area.Pavel Pisa2019-02-13
| | | | | | | | | | Address under 0xc0000000 corresponds to typical Linux stack on 32-bit systems. If SP is initialized to 0x00000000 then it can overwrite programs tarting at RAM begin and overflow to top of physical address-space which is reserved for uncached peripherals. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Include simple serial port terminal and prepare empty peripheral dock.Pavel Pisa2019-02-13
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add speed option to run core for time chunks without visualization.Pavel Pisa2019-02-13
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add signals and multiplexers for ALU inputs forwarding.Pavel Pisa2019-02-12
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add ELF library even to the final executables linking to allow build with ↵Pavel Pisa2019-02-12
| | | | | | static machine lib. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Make memory and program listing editable.Pavel Pisa2019-02-12
| | | | | | Instruction parsing is rough and does not support branch offset computation. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement LRU as simple priority queue with linear insert sort.Pavel Pisa2019-02-12
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add debug access to rword and friends to allow read data through cache ↵Pavel Pisa2019-02-12
| | | | | | | | without disturbing statistic. This allows to switch view between CPU and raw memory content. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Display red background for instruction causing exception and skip HW ↵Pavel Pisa2019-02-11
| | | | | | | | | | breakpoint for first cycle after resume. Instruction for stage is updated when given stage is flushed as well. But other signals are left intact, it is duty of memory stage to discard effect of instruction causing interrupt. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Basic "hardware" breakpoints support implemented.Pavel Pisa2019-02-11
| | | | | | | | | | It works like real inserted breakpoint on hardware. Breakpoint has to be removed to allow code continue because else instruction is refetch and breakpoint triggers again. The single step function should resolve temporal masking of the breakpoint. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Prepare core for "hardware" breakpoints support and add signals to follow ↵Pavel Pisa2019-02-11
| | | | | | stages. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct build for LLVM.Fanda Vacek2019-02-09
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* Minimal implementation of RDHWR to support dummy TLS region.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Move computation of cache row, column and tag to single inline function.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement SYNCI as complete cache flush.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Accept SINC and SINCI instructions and flush even instruction cache on CACHE ↵Pavel Pisa2019-02-08
| | | | | | | | | | opcode. Because individual cache maintenance operations are not decoded, be on safe side and flush all caches when CACHE operation is processed, Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Document InstructionFlags meaning and remove unused IMF_MEM_STORE.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement even deprecated BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, ↵Pavel Pisa2019-02-08
| | | | | | | | BGEZALL. GCC generates these opcodes for default compilation mode. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Make function to register exception handler accessible from outside.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement LL and SC as simple load and store word. SC returns 1 unconditionally.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add write and read notification to the simple peripheral component.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Exception handlers require even PC of the jump or branch instruction before ↵Pavel Pisa2019-02-07
| | | | | | | | | | | delay slot. When exception occurs at instruction in delay slot, the address of branch/delay instruction is stored to EPC instead of address of instruction causing the exception. So that address has to be delivered to exception handling object. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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