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* Display rs, rt, rd and write register number in all stages.Pavel Pisa2019-01-31
* Correct processing of ORI, ANDI, XORI instructions which require zero-extende...Pavel Pisa2019-01-31
* Do not replace rt by forward if instruction in T_R or store.Pavel Pisa2019-01-30
* Display execution stage forward signals in the view.Pavel Pisa2019-01-30
* Correct hazards processing.Pavel Pisa2019-01-30
* Add few more labelsKarel Kočí2018-05-24
* Add buses statis viewsKarel Kočí2018-05-24
* Add cache view rendererKarel Kočí2018-05-23
* Add cache statisticsKarel Kočí2018-05-23
* Fix load and store instructionsKarel Kočí2018-05-02
* Initial implementation of cache viewKarel Kočí2018-04-17
* Change presetsKarel Kočí2018-04-15
* Show cache statistics in Memory block in coreviewKarel Kočí2018-04-15
* Drop quick jump buttons from memory viewKarel Kočí2018-04-10
* Fix some instruction string representationKarel Kočí2018-04-08
* Change string format for some instructionKarel Kočí2018-04-08
* Implement LUIKarel Kočí2018-04-08
* Implement sync for memoryKarel Kočí2018-04-08
* Ensure that set, block and assoc. is in minimum oneKarel Kočí2018-04-08
* Integrate cache with rest of the machine coreKarel Kočí2018-04-08
* Add associative cacheKarel Kočí2018-04-08
* Drop unneeded mask in memory implementationKarel Kočí2018-04-07
* Add initial implementatio of cachesKarel Kočí2018-04-07
* Just note that we are checking endianity automaticallyKarel Kočí2018-04-05
* Use whole words in memoryKarel Kočí2018-04-05
* Fix forwarding checker for I and J and S* instructionsKarel Kočí2018-03-06
* Implement Cache configurationKarel Kočí2018-03-06
* Forward from execute stage to decode stage latchKarel Kočí2018-02-14
* Do empty fetch stage to report fetch even if we stallKarel Kočí2018-02-14
* Another swap in instruction decodingKarel Kočí2018-02-14
* Swap rs and rt in I instructons decodingKarel Kočí2018-02-14
* Fix signextend in coreKarel Kočí2018-02-14
* Fix program loadingKarel Kočí2018-02-14
* Various graphics tweaksKarel Kočí2018-01-27
* Add focus function to memory viewKarel Kočí2018-01-25
* Compile with debug symbols for DEBUG configKarel Kočí2018-01-25
* Add instruction view to single coreKarel Kočí2018-01-21
* Fix Pipelined core not to accept hazard unit configurationKarel Kočí2018-01-17
* Print I instruction immediate field in hexaKarel Kočí2018-01-17
* Update how configuration is handled in newdialogKarel Kočí2018-01-17
* Cleanup some todos in codeKarel Kočí2018-01-15
* Emit byte_change when byte is written to memoryKarel Kočí2018-01-15
* Fix program loader testKarel Kočí2018-01-15
* Fix SRA and SRAV instructionsKarel Kočí2018-01-15
* Implement hazard unitKarel Kočí2018-01-15
* Reverse translate NOP correctlyKarel Kočí2018-01-15
* Change how we configure cache and configure hazard unitKarel Kočí2018-01-15
* Allow instruction trace from any stageKarel Kočí2018-01-11
* Add ability to get specific core type from qtmipsmachineKarel Kočí2018-01-08
* Implement machine restartKarel Kočí2018-01-05
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