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* Add license to the source files.Pavel Pisa2019-02-04
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct write-back cache behavior.Pavel Pisa2019-02-04
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct memory view updates for uncached and write-through case.Pavel Pisa2019-02-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement BREAK instruction to stop continuous execution.Pavel Pisa2019-02-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement instructions MULT, MULTU, DIV, DIVU.Pavel Pisa2019-02-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ ↵Pavel Pisa2019-02-02
| | | | | | | | | | | instructions. The previous code worked by chance only because decode has been fully processed including forwarding from M and W before PC processing started. But in real hardware the PC processing runs in parallel with ALU and cannot read its results in the same cycle. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Include test for jump and link processing.Pavel Pisa2019-02-02
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add test for forwarding in ALU operations.Pavel Pisa2019-02-02
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct ALU test for SUB exception.Pavel Pisa2019-02-02
| | | | | | | | | | | | The operation 3 - 4 = 1 is legal integer arithmetic operation. Changed to 0x80000003 - 4 = 0x7fffffff 2147483651 - 4 = 2147483647 which overflows. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Include support for JALR support.Pavel Pisa2019-01-31
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Initial support for JAL.Pavel Pisa2019-01-31
| | | | | | | The JR, BEQ, BNE are most probably incorrect still. There is missing forwarding for pipelined execution. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct signed arithmetic overflow exception.Pavel Pisa2019-01-31
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Display rs, rt, rd and write register number in all stages.Pavel Pisa2019-01-31
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct processing of ORI, ANDI, XORI instructions which require ↵Pavel Pisa2019-01-31
| | | | | | zero-extended immediate. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Do not replace rt by forward if instruction in T_R or store.Pavel Pisa2019-01-30
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Display execution stage forward signals in the view.Pavel Pisa2019-01-30
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct hazards processing.Pavel Pisa2019-01-30
| | | | | | | | The shorter loop has priority. This is achieved by later processing when it replaces possible result from longer loop over W stage. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add few more labelsKarel Kočí2018-05-24
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* Add buses statis viewsKarel Kočí2018-05-24
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* Add cache view rendererKarel Kočí2018-05-23
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* Add cache statisticsKarel Kočí2018-05-23
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* Fix load and store instructionsKarel Kočí2018-05-02
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* Initial implementation of cache viewKarel Kočí2018-04-17
| | | | It needs some more work to look nice but it already works.
* Change presetsKarel Kočí2018-04-15
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* Show cache statistics in Memory block in coreviewKarel Kočí2018-04-15
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* Drop quick jump buttons from memory viewKarel Kočí2018-04-10
| | | | | They are not implemented and even if they would they usage would be little bit funky as they would jump by internal amount of page memory.
* Fix some instruction string representationKarel Kočí2018-04-08
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* Change string format for some instructionKarel Kočí2018-04-08
| | | | This makes our string format closer to original assembler.
* Implement LUIKarel Kočí2018-04-08
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* Implement sync for memoryKarel Kočí2018-04-08
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* Ensure that set, block and assoc. is in minimum oneKarel Kočí2018-04-08
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* Integrate cache with rest of the machine coreKarel Kočí2018-04-08
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* Add associative cacheKarel Kočí2018-04-08
| | | | Not fully tested yet.
* Drop unneeded mask in memory implementationKarel Kočí2018-04-07
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* Add initial implementatio of cachesKarel Kočí2018-04-07
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* Just note that we are checking endianity automaticallyKarel Kočí2018-04-05
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* Use whole words in memoryKarel Kočí2018-04-05
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* Fix forwarding checker for I and J and S* instructionsKarel Kočí2018-03-06
| | | | THere are exceptions when we care about forwarding and when we don't.
* Implement Cache configurationKarel Kočí2018-03-06
| | | | This commit implements both cache configuration for machine and for gui.
* Forward from execute stage to decode stage latchKarel Kočí2018-02-14
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* Do empty fetch stage to report fetch even if we stallKarel Kočí2018-02-14
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* Another swap in instruction decodingKarel Kočí2018-02-14
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* Swap rs and rt in I instructons decodingKarel Kočí2018-02-14
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* Fix signextend in coreKarel Kočí2018-02-14
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* Fix program loadingKarel Kočí2018-02-14
| | | | First section was ignored
* Various graphics tweaksKarel Kočí2018-01-27
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* Add focus function to memory viewKarel Kočí2018-01-25
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* Compile with debug symbols for DEBUG configKarel Kočí2018-01-25
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* Add instruction view to single coreKarel Kočí2018-01-21
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* Fix Pipelined core not to accept hazard unit configurationKarel Kočí2018-01-17
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