qtmips - MIPS CPU emulator for education purposes

	Commit message (Collapse)	Author	Age
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*	Correct memory view updates for uncached and write-through case.	Pavel Pisa	2019-02-03
\| \| \| \|	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Implement BREAK instruction to stop continuous execution.	Pavel Pisa	2019-02-03
\| \| \| \|	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Implement instructions MULT, MULTU, DIV, DIVU.	Pavel Pisa	2019-02-03
\| \| \| \|	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ ↵	Pavel Pisa	2019-02-02
\| \| \| \| \| \| \| \| \| \| \|	instructions. The previous code worked by chance only because decode has been fully processed including forwarding from M and W before PC processing started. But in real hardware the PC processing runs in parallel with ALU and cannot read its results in the same cycle. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Include test for jump and link processing.	Pavel Pisa	2019-02-02
\| \| \| \|	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Add test for forwarding in ALU operations.	Pavel Pisa	2019-02-02
\| \| \| \|	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Correct ALU test for SUB exception.	Pavel Pisa	2019-02-02
\| \| \| \| \| \| \| \| \| \| \| \|	The operation 3 - 4 = 1 is legal integer arithmetic operation. Changed to 0x80000003 - 4 = 0x7fffffff 2147483651 - 4 = 2147483647 which overflows. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Include support for JALR support.	Pavel Pisa	2019-01-31
\| \| \| \|	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Initial support for JAL.	Pavel Pisa	2019-01-31
\| \| \| \| \| \| \|	The JR, BEQ, BNE are most probably incorrect still. There is missing forwarding for pipelined execution. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Correct signed arithmetic overflow exception.	Pavel Pisa	2019-01-31
\| \| \| \|	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Display rs, rt, rd and write register number in all stages.	Pavel Pisa	2019-01-31
\| \| \| \|	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Correct processing of ORI, ANDI, XORI instructions which require ↵	Pavel Pisa	2019-01-31
\| \| \| \| \| \|	zero-extended immediate. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Do not replace rt by forward if instruction in T_R or store.	Pavel Pisa	2019-01-30
\| \| \| \|	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Display execution stage forward signals in the view.	Pavel Pisa	2019-01-30
\| \| \| \|	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Correct hazards processing.	Pavel Pisa	2019-01-30
\| \| \| \| \| \| \| \|	The shorter loop has priority. This is achieved by later processing when it replaces possible result from longer loop over W stage. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Add few more labels	Karel Kočí	2018-05-24
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*	Add buses statis views	Karel Kočí	2018-05-24
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*	Add cache view renderer	Karel Kočí	2018-05-23
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*	Add cache statistics	Karel Kočí	2018-05-23
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*	Fix load and store instructions	Karel Kočí	2018-05-02
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*	Initial implementation of cache view	Karel Kočí	2018-04-17
\| \| \| \|	It needs some more work to look nice but it already works.
*	Change presets	Karel Kočí	2018-04-15
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*	Show cache statistics in Memory block in coreview	Karel Kočí	2018-04-15
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*	Drop quick jump buttons from memory view	Karel Kočí	2018-04-10
\| \| \| \| \|	They are not implemented and even if they would they usage would be little bit funky as they would jump by internal amount of page memory.
*	Fix some instruction string representation	Karel Kočí	2018-04-08
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*	Change string format for some instruction	Karel Kočí	2018-04-08
\| \| \| \|	This makes our string format closer to original assembler.
*	Implement LUI	Karel Kočí	2018-04-08
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*	Implement sync for memory	Karel Kočí	2018-04-08
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*	Ensure that set, block and assoc. is in minimum one	Karel Kočí	2018-04-08
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*	Integrate cache with rest of the machine core	Karel Kočí	2018-04-08
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*	Add associative cache	Karel Kočí	2018-04-08
\| \| \| \|	Not fully tested yet.
*	Drop unneeded mask in memory implementation	Karel Kočí	2018-04-07
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*	Add initial implementatio of caches	Karel Kočí	2018-04-07
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*	Just note that we are checking endianity automatically	Karel Kočí	2018-04-05
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*	Use whole words in memory	Karel Kočí	2018-04-05
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*	Fix forwarding checker for I and J and S* instructions	Karel Kočí	2018-03-06
\| \| \| \|	THere are exceptions when we care about forwarding and when we don't.
*	Implement Cache configuration	Karel Kočí	2018-03-06
\| \| \| \|	This commit implements both cache configuration for machine and for gui.
*	Forward from execute stage to decode stage latch	Karel Kočí	2018-02-14
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*	Do empty fetch stage to report fetch even if we stall	Karel Kočí	2018-02-14
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*	Another swap in instruction decoding	Karel Kočí	2018-02-14
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*	Swap rs and rt in I instructons decoding	Karel Kočí	2018-02-14
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*	Fix signextend in core	Karel Kočí	2018-02-14
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*	Fix program loading	Karel Kočí	2018-02-14
\| \| \| \|	First section was ignored
*	Various graphics tweaks	Karel Kočí	2018-01-27
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*	Add focus function to memory view	Karel Kočí	2018-01-25
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*	Compile with debug symbols for DEBUG config	Karel Kočí	2018-01-25
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*	Add instruction view to single core	Karel Kočí	2018-01-21
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*	Fix Pipelined core not to accept hazard unit configuration	Karel Kočí	2018-01-17
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*	Print I instruction immediate field in hexa	Karel Kočí	2018-01-17
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*	Update how configuration is handled in newdialog	Karel Kočí	2018-01-17
\| \| \| \| \| \|	In previous implementation were dependencies described on two places. In NewDialog and in MachineConfig. Now NewDialog sets options in MachineConfig and configuration is then applied to NewDialog.