qtmips - MIPS CPU emulator for education purposes

	Commit message (Collapse)	Author	Age
*	Integrate cache with rest of the machine core	Karel Kočí	2018-04-08
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*	Fix signextend in core	Karel Kočí	2018-02-14
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*	Fix SRA and SRAV instructions	Karel Kočí	2018-01-15
\| \| \| \| \| \|	This implementation is correct one but there is no guarantee that it will work with all compilers so we should always check on given platform that tests pass (and potentially fix it).
*	Allow delay slot disable for non-pipelined core	Karel Kočí	2018-01-03
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*	Put qtmips_machine to machine namespace	Karel Kočí	2017-12-17
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*	Fix test for JR	Karel Kočí	2017-12-12
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*	Implement some store and load instructions	Karel Kočí	2017-12-12
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*	Implement branch and jump instructions	Karel Kočí	2017-12-12
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*	Add crude implementation of MOV* instructions	Karel Kočí	2017-11-25
\| \| \| \|	I don't like how it's implemented but I have no other idea atm.
*	Implement instructions for moving from and to HI and LO registers	Karel Kočí	2017-11-25
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*	Test pipelined core	Karel Kočí	2017-11-25
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*	Implement some logical operations	Karel Kočí	2017-11-21
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*	Implement some immediate arithmetic instructions	Karel Kočí	2017-11-21
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*	Implement tests for few more arithmetic instructions	Karel Kočí	2017-11-21
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*	Implement and test ADD	Karel Kočí	2017-11-21
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*	Add possibility to compare memory and registers state	Karel Kočí	2017-11-21
\| \| \| \| \| \|	For core testing we want to compare whole memory and registers. Registers are pretty simple but in case of memory it is some what more complicated and required its own tests to be sure that it works.
*	Another huge pile of work for about two months	Karel Kočí	2017-11-19
\| \| \| \| \| \|	Well I should commit every change instead of this madness. I am not documenting changes as all this is just improvements and implementation progression.
*	Just something I had stagged	Karel Kočí	2017-11-19