qtmips - MIPS CPU emulator for education purposes

	Commit message (Collapse)	Author	Age
*	Pass arithmetic exception trough pipeline and implement trap support and ↵	Pavel Pisa	2019-02-17
\| \| \| \| \| \|	instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Multiply and accumulate and CLZ/CLO operations added.	Pavel Pisa	2019-02-15
\| \| \| \|	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Implement EXT instruction used in GLIBC startup.	Pavel Pisa	2019-02-15
\| \| \| \| \| \|	It requires one more field to pass to ALU. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Core: move complex memory operation to own function and implement LWL, LWR, ↵	Pavel Pisa	2019-02-15
\| \| \| \| \| \| \| \|	SWL, SWR. The move makes basic memory stage processing more readable. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Implement MUL operation which stores result to the register.	Pavel Pisa	2019-02-14
\| \| \| \|	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Prepare core for "hardware" breakpoints support and add signals to follow ↵	Pavel Pisa	2019-02-11
\| \| \| \| \| \|	stages. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Minimal implementation of RDHWR to support dummy TLS region.	Pavel Pisa	2019-02-08
\| \| \| \|	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Implement LL and SC as simple load and store word. SC returns 1 unconditionally.	Pavel Pisa	2019-02-08
\| \| \| \|	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Added method to retrieve memory location status.	Pavel Pisa	2019-02-07
\| \| \| \| \| \| \|	It can inform if given location is cached or if given range is invalid in address space. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Implement BSHFL instruction and ignore RDHWR instruction.	Pavel Pisa	2019-02-07
\|
*	Remove dependency of ALU operation encoding on MIPS instruction format.	Pavel Pisa	2019-02-07
\| \| \| \|	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Implemented base for exception handling.	Pavel Pisa	2019-02-06
\| \| \| \| \| \| \| \| \| \| \| \| \| \|	Memory stage is chosen to be exception commit stage. Instructions flow postponed and stages holding following instructions are cleaned. Processing of syscall at decode stage as jump to the handler would be better solution in real hardware but for future emulated syscalls it is better to reach consistent state of registers. Memory access caused exceptions would require cleanup even in real hardware. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Reorganize PC handling and implement full REGIMM decode.	Pavel Pisa	2019-02-05
\| \| \| \|	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Unified instructions table and access type move to machinedefs.h .	Pavel Pisa	2019-02-04
	This allows to specify requirement for RS and RD on instruction basis even for T_R / ALU instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>