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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Memory stage is chosen to be exception commit stage.
Instructions flow postponed and stages holding following
instructions are cleaned. Processing of syscall at decode
stage as jump to the handler would be better solution
in real hardware but for future emulated syscalls
it is better to reach consistent state of registers.
Memory access caused exceptions would require cleanup
even in real hardware.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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This allows to specify requirement for RS and RD on instruction
basis even for T_R / ALU instructions.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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