| Commit message (Collapse) | Author | Age |
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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independent.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Remaining are MOVZ and MOVN in the execution phase
and all branch and jump operations in handle_pc().
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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This allows to specify requirement for RS and RD on instruction
basis even for T_R / ALU instructions.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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THere are exceptions when we care about forwarding and when we don't.
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In reality this internally allows us to see stages even it we are not
using pipelining but that is hidden from outside simply to not confuse
user.
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This is rude implementation. We always print all fields. In future we
should add flags to set what fields should be hidden on per instruction
bases.
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For core testing we want to compare whole memory and registers.
Registers are pretty simple but in case of memory it is some what more
complicated and required its own tests to be sure that it works.
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Well I should commit every change instead of this madness. I am not
documenting changes as all this is just improvements and implementation
progression.
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Adding work done so far.
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