| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | Implemented coprocessor 0 registers access and register EPC and Cause set by ↵ | Pavel Pisa | 2019-03-04 |
| | | | | | | | exception. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement ROTR and ROTRV and full decode of WSBH, SEB and SEH. | Pavel Pisa | 2019-02-24 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct ADD operation to map to ALU variant with overflow checking. | Pavel Pisa | 2019-02-18 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Ignore LWC1, LWD1, SWC1 and SDC1 instructions. | Pavel Pisa | 2019-02-17 |
| | | | | | | | This allows to use MUSL Lib C printf and scanf implementations. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Pass arithmetic exception trough pipeline and implement trap support and ↵ | Pavel Pisa | 2019-02-17 |
| | | | | | | | instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Multiply and accumulate and CLZ/CLO operations added. | Pavel Pisa | 2019-02-15 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement EXT instruction used in GLIBC startup. | Pavel Pisa | 2019-02-15 |
| | | | | | | | It requires one more field to pass to ALU. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Core: move complex memory operation to own function and implement LWL, LWR, ↵ | Pavel Pisa | 2019-02-15 |
| | | | | | | | | | SWL, SWR. The move makes basic memory stage processing more readable. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Fill the rest of ALU opcode table to file all 64 entries. | Pavel Pisa | 2019-02-14 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Ignore PREF instruction. | Pavel Pisa | 2019-02-14 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement MUL operation which stores result to the register. | Pavel Pisa | 2019-02-14 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Make memory and program listing editable. | Pavel Pisa | 2019-02-12 |
| | | | | | | | Instruction parsing is rough and does not support branch offset computation. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Minimal implementation of RDHWR to support dummy TLS region. | Pavel Pisa | 2019-02-08 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement SYNCI as complete cache flush. | Pavel Pisa | 2019-02-08 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Accept SINC and SINCI instructions and flush even instruction cache on CACHE ↵ | Pavel Pisa | 2019-02-08 |
| | | | | | | | | | | | opcode. Because individual cache maintenance operations are not decoded, be on safe side and flush all caches when CACHE operation is processed, Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Document InstructionFlags meaning and remove unused IMF_MEM_STORE. | Pavel Pisa | 2019-02-08 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement even deprecated BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, ↵ | Pavel Pisa | 2019-02-08 |
| | | | | | | | | | BGEZALL. GCC generates these opcodes for default compilation mode. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement LL and SC as simple load and store word. SC returns 1 unconditionally. | Pavel Pisa | 2019-02-08 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct display of jump and branch instructions. | Pavel Pisa | 2019-02-07 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement BSHFL instruction and ignore RDHWR instruction. | Pavel Pisa | 2019-02-07 |
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| * | Remove dependency of ALU operation encoding on MIPS instruction format. | Pavel Pisa | 2019-02-07 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct BLTZAL and BGEZAL execution to pass unmodified value to R31. | Pavel Pisa | 2019-02-07 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implemented base for exception handling. | Pavel Pisa | 2019-02-06 |
| | | | | | | | | | | | | | | | Memory stage is chosen to be exception commit stage. Instructions flow postponed and stages holding following instructions are cleaned. Processing of syscall at decode stage as jump to the handler would be better solution in real hardware but for future emulated syscalls it is better to reach consistent state of registers. Memory access caused exceptions would require cleanup even in real hardware. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct registers order in conversion to text for branch instructions. | Pavel Pisa | 2019-02-06 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Reorganize PC handling and implement full REGIMM decode. | Pavel Pisa | 2019-02-05 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct shift operation and make ALU_OP_MOVZ and ALU_OP_MOVN encoding ↵ | Pavel Pisa | 2019-02-05 |
| | | | | | | | independent. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Make instruction to text conversion more generic. | Pavel Pisa | 2019-02-05 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Rewrite instruction decoding to be generic and mostly architecture independent. | Pavel Pisa | 2019-02-05 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Remove almost all direct access to opcode and function from the core. | Pavel Pisa | 2019-02-04 |
| | | | | | | | | Remaining are MOVZ and MOVN in the execution phase and all branch and jump operations in handle_pc(). Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Take into account actual requirements for rs, rt and rd write for individual ↵ | Pavel Pisa | 2019-02-04 |
| | | | | | | | instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Unified instructions table and access type move to machinedefs.h . | Pavel Pisa | 2019-02-04 |
| | | | | | | | | This allows to specify requirement for RS and RD on instruction basis even for T_R / ALU instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Primitive implementation of cache instruction. | Pavel Pisa | 2019-02-04 |
| | | | | | | | | When any variant of cache instruction is detected flush and invalidate whole data cache. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Add license to the source files. | Pavel Pisa | 2019-02-04 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement BREAK instruction to stop continuous execution. | Pavel Pisa | 2019-02-03 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement instructions MULT, MULTU, DIV, DIVU. | Pavel Pisa | 2019-02-03 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Fix some instruction string representation | Karel Kočí | 2018-04-08 |
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| * | Change string format for some instruction | Karel Kočí | 2018-04-08 |
| | | | | | This makes our string format closer to original assembler. | ||
| * | Fix forwarding checker for I and J and S* instructions | Karel Kočí | 2018-03-06 |
| | | | | | THere are exceptions when we care about forwarding and when we don't. | ||
| * | Another swap in instruction decoding | Karel Kočí | 2018-02-14 |
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| * | Swap rs and rt in I instructons decoding | Karel Kočí | 2018-02-14 |
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| * | Various graphics tweaks | Karel Kočí | 2018-01-27 |
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| * | Print I instruction immediate field in hexa | Karel Kočí | 2018-01-17 |
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| * | Reverse translate NOP correctly | Karel Kočí | 2018-01-15 |
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| * | Allow instruction trace from any stage | Karel Kočí | 2018-01-11 |
| | | | | | | | In reality this internally allows us to see stages even it we are not using pipelining but that is hidden from outside simply to not confuse user. | ||
| * | Initial implementation of reverse instruction conversion | Karel Kočí | 2018-01-03 |
| | | | | | | | This is rude implementation. We always print all fields. In future we should add flags to set what fields should be hidden on per instruction bases. | ||
| * | Put qtmips_machine to machine namespace | Karel Kočí | 2017-12-17 |
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| * | Revert "Suppress some warning" | Karel Kočí | 2017-12-17 |
| | | | | | This reverts commit 5bf637a429bbcf09092b8d189010c50d61c3562f. | ||
| * | Suppress some warning | Karel Kočí | 2017-12-12 |
| | | | | | | You can call it a fix but in reality it has same effect but I accept that this is better. | ||
| * | Test pipelined core | Karel Kočí | 2017-11-25 |
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| * | Implement tests for few more arithmetic instructions | Karel Kočí | 2017-11-21 |
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