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path: root/qtmips_machine/instruction.cpp
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* Simple assembler moved to separate class which is independent on Qt GUI API.Pavel Pisa2019-07-17
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Instructions update and encoding enhanced.Pavel Pisa2019-07-03
| | | | | | | | | Be permissive when signed argument is defined as unsigned value near 2^32 because it is usual way how the negative arguments are encoded on 32-bit system. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Use explicitly declared empty stringlist for instructions without arguments.Pavel Pisa2019-07-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Allow underscore in labels.Pavel Pisa2019-07-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add option to parse and show symbolic registers names.Pavel Pisa2019-07-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Allow spaces in middle of assembler arguments and report errors.Pavel Pisa2019-07-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Extend instruction parsing to accept numeric value continuing by expression.Pavel Pisa2019-07-02
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add binary complement operation to the parser.Pavel Pisa2019-07-02
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Simple highlighter for assembly language added.Pavel Pisa2019-07-02
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Teach simple embedded assembler .orig and .word directives.Pavel Pisa2019-07-02
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Change instruction parsing to allow multiple words pseudo-operations.Pavel Pisa2019-07-02
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Evaluation of symbolic expressions in assembler added.Pavel Pisa2019-07-02
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Minimal prototype of integrated assembler.Pavel Pisa2019-07-01
| | | | | | | The labels are parsed and stored into symbol table but expressions dependent on symbols values are not evaluated. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Convert QString to C string character by character, std::strtol{l} fails ↵Pavel Pisa2019-06-26
| | | | | | | | | | under some circumstances. It seems that under Emscripten build and sometimes even under Windows build the conversion QString.toLatin1().data() does not guarantee well formed null terminated C string. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Suppress warning where case fall-through is intentional.Pavel Pisa2019-03-06
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct parsing of register + offset operands, i.e., LW and SW.Pavel Pisa2019-03-06
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Try the strict check of encoded instructions and relax break and other.Pavel Pisa2019-03-05
| | | | | | | Some instructions can have fields to be used by operating system or for error reporting by user. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Complete revamp of disassembler and assembler arguments processing.Pavel Pisa2019-03-05
| | | | | | | | | | | | | | | | | | | | | Instructions description in instruction.cpp has been pragmatically augmented by tool based on Python MIPS simulator, hazards analyzer https://github.com/ppisa/apo-simarch That code has been originally distilled from from GNU binutils sources. Implementation is now inline with my original proposal Previous solution gets untenable with more complex instructions and its complexity would grow extremely. MIPS instruction set with coprocessor instructions which use sel field, rd used as index, rt as destination and other peculiarities in newer versions cannot be processed based on basic CPU control signals. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented coprocessor 0 registers access and register EPC and Cause set by ↵Pavel Pisa2019-03-04
| | | | | | exception. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement ROTR and ROTRV and full decode of WSBH, SEB and SEH.Pavel Pisa2019-02-24
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct ADD operation to map to ALU variant with overflow checking.Pavel Pisa2019-02-18
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Ignore LWC1, LWD1, SWC1 and SDC1 instructions.Pavel Pisa2019-02-17
| | | | | | This allows to use MUSL Lib C printf and scanf implementations. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Pass arithmetic exception trough pipeline and implement trap support and ↵Pavel Pisa2019-02-17
| | | | | | instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Multiply and accumulate and CLZ/CLO operations added.Pavel Pisa2019-02-15
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement EXT instruction used in GLIBC startup.Pavel Pisa2019-02-15
| | | | | | It requires one more field to pass to ALU. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Core: move complex memory operation to own function and implement LWL, LWR, ↵Pavel Pisa2019-02-15
| | | | | | | | SWL, SWR. The move makes basic memory stage processing more readable. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Fill the rest of ALU opcode table to file all 64 entries.Pavel Pisa2019-02-14
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Ignore PREF instruction.Pavel Pisa2019-02-14
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement MUL operation which stores result to the register.Pavel Pisa2019-02-14
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Make memory and program listing editable.Pavel Pisa2019-02-12
| | | | | | Instruction parsing is rough and does not support branch offset computation. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Minimal implementation of RDHWR to support dummy TLS region.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement SYNCI as complete cache flush.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Accept SINC and SINCI instructions and flush even instruction cache on CACHE ↵Pavel Pisa2019-02-08
| | | | | | | | | | opcode. Because individual cache maintenance operations are not decoded, be on safe side and flush all caches when CACHE operation is processed, Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Document InstructionFlags meaning and remove unused IMF_MEM_STORE.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement even deprecated BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, ↵Pavel Pisa2019-02-08
| | | | | | | | BGEZALL. GCC generates these opcodes for default compilation mode. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement LL and SC as simple load and store word. SC returns 1 unconditionally.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct display of jump and branch instructions.Pavel Pisa2019-02-07
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement BSHFL instruction and ignore RDHWR instruction.Pavel Pisa2019-02-07
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* Remove dependency of ALU operation encoding on MIPS instruction format.Pavel Pisa2019-02-07
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct BLTZAL and BGEZAL execution to pass unmodified value to R31.Pavel Pisa2019-02-07
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented base for exception handling.Pavel Pisa2019-02-06
| | | | | | | | | | | | | | Memory stage is chosen to be exception commit stage. Instructions flow postponed and stages holding following instructions are cleaned. Processing of syscall at decode stage as jump to the handler would be better solution in real hardware but for future emulated syscalls it is better to reach consistent state of registers. Memory access caused exceptions would require cleanup even in real hardware. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct registers order in conversion to text for branch instructions.Pavel Pisa2019-02-06
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Reorganize PC handling and implement full REGIMM decode.Pavel Pisa2019-02-05
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct shift operation and make ALU_OP_MOVZ and ALU_OP_MOVN encoding ↵Pavel Pisa2019-02-05
| | | | | | independent. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Make instruction to text conversion more generic.Pavel Pisa2019-02-05
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Rewrite instruction decoding to be generic and mostly architecture independent.Pavel Pisa2019-02-05
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Remove almost all direct access to opcode and function from the core.Pavel Pisa2019-02-04
| | | | | | | Remaining are MOVZ and MOVN in the execution phase and all branch and jump operations in handle_pc(). Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Take into account actual requirements for rs, rt and rd write for individual ↵Pavel Pisa2019-02-04
| | | | | | instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Unified instructions table and access type move to machinedefs.h .Pavel Pisa2019-02-04
| | | | | | | This allows to specify requirement for RS and RD on instruction basis even for T_R / ALU instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Primitive implementation of cache instruction.Pavel Pisa2019-02-04
| | | | | | | When any variant of cache instruction is detected flush and invalidate whole data cache. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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