| Commit message (Expand) | Author | Age |
|---|
| * | Resolve some memory leaks found by Valgrind. | Pavel Pisa | 2019-02-06 |
| * | Reorganize PC handling and implement full REGIMM decode. | Pavel Pisa | 2019-02-05 |
| * | Correct shift operation and make ALU_OP_MOVZ and ALU_OP_MOVN encoding indepen... | Pavel Pisa | 2019-02-05 |
| * | Rewrite instruction decoding to be generic and mostly architecture independent. | Pavel Pisa | 2019-02-05 |
| * | Remove almost all direct access to opcode and function from the core. | Pavel Pisa | 2019-02-04 |
| * | Take into account actual requirements for rs, rt and rd write for individual ... | Pavel Pisa | 2019-02-04 |
| * | Unified instructions table and access type move to machinedefs.h . | Pavel Pisa | 2019-02-04 |
| * | Primitive implementation of cache instruction. | Pavel Pisa | 2019-02-04 |
| * | Add license to the source files. | Pavel Pisa | 2019-02-04 |
| * | Implement BREAK instruction to stop continuous execution. | Pavel Pisa | 2019-02-03 |
| * | Implement instructions MULT, MULTU, DIV, DIVU. | Pavel Pisa | 2019-02-03 |
| * | Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ inst... | Pavel Pisa | 2019-02-02 |
| * | Include support for JALR support. | Pavel Pisa | 2019-01-31 |
| * | Initial support for JAL. | Pavel Pisa | 2019-01-31 |
| * | Display rs, rt, rd and write register number in all stages. | Pavel Pisa | 2019-01-31 |
| * | Correct processing of ORI, ANDI, XORI instructions which require zero-extende... | Pavel Pisa | 2019-01-31 |
| * | Do not replace rt by forward if instruction in T_R or store. | Pavel Pisa | 2019-01-30 |
| * | Display execution stage forward signals in the view. | Pavel Pisa | 2019-01-30 |
| * | Correct hazards processing. | Pavel Pisa | 2019-01-30 |
| * | Add few more labels | Karel Kočí | 2018-05-24 |
| * | Add buses statis views | Karel Kočí | 2018-05-24 |
| * | Fix load and store instructions | Karel Kočí | 2018-05-02 |
| * | Implement LUI | Karel Kočí | 2018-04-08 |
| * | Implement sync for memory | Karel Kočí | 2018-04-08 |
| * | Integrate cache with rest of the machine core | Karel Kočí | 2018-04-08 |
| * | Fix forwarding checker for I and J and S* instructions | Karel Kočí | 2018-03-06 |
| * | Forward from execute stage to decode stage latch | Karel Kočí | 2018-02-14 |
| * | Do empty fetch stage to report fetch even if we stall | Karel Kočí | 2018-02-14 |
| * | Fix signextend in core | Karel Kočí | 2018-02-14 |
| * | Add instruction view to single core | Karel Kočí | 2018-01-21 |
| * | Cleanup some todos in code | Karel Kočí | 2018-01-15 |
| * | Implement hazard unit | Karel Kočí | 2018-01-15 |
| * | Allow instruction trace from any stage | Karel Kočí | 2018-01-11 |
| * | Implement machine restart | Karel Kočí | 2018-01-05 |
| * | Allow delay slot disable for non-pipelined core | Karel Kočí | 2018-01-03 |
| * | Add trace-feth to qtmips_cli | Karel Kočí | 2018-01-03 |
| * | Put qtmips_machine to machine namespace | Karel Kočí | 2017-12-17 |
| * | Implement some store and load instructions | Karel Kočí | 2017-12-12 |
| * | Fix immediate alu operation | Karel Kočí | 2017-12-12 |
| * | Implement branch and jump instructions | Karel Kočí | 2017-12-12 |
| * | Add crude implementation of MOV* instructions | Karel Kočí | 2017-11-25 |
| * | Implement instructions for moving from and to HI and LO registers | Karel Kočí | 2017-11-25 |
| * | Test pipelined core | Karel Kočí | 2017-11-25 |
| * | Implement some logical operations | Karel Kočí | 2017-11-21 |
| * | Implement some immediate arithmetic instructions | Karel Kočí | 2017-11-21 |
| * | Implement and test ADD | Karel Kočí | 2017-11-21 |
| * | Another huge pile of work for about two months | Karel Kočí | 2017-11-19 |
| * | Initial commit | Karel Kočí | 2017-08-30 |
