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path: root/qtmips_machine/core.cpp
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* Minimal implementation of RDHWR to support dummy TLS region.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement SYNCI as complete cache flush.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Accept SINC and SINCI instructions and flush even instruction cache on CACHE ↵Pavel Pisa2019-02-08
| | | | | | | | | | opcode. Because individual cache maintenance operations are not decoded, be on safe side and flush all caches when CACHE operation is processed, Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement even deprecated BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, ↵Pavel Pisa2019-02-08
| | | | | | | | BGEZALL. GCC generates these opcodes for default compilation mode. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement LL and SC as simple load and store word. SC returns 1 unconditionally.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Exception handlers require even PC of the jump or branch instruction before ↵Pavel Pisa2019-02-07
| | | | | | | | | | | delay slot. When exception occurs at instruction in delay slot, the address of branch/delay instruction is stored to EPC instead of address of instruction causing the exception. So that address has to be delivered to exception handling object. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add address to emitted instruction to allow its use for branch address decoding.Pavel Pisa2019-02-07
| | | | | | | | The new Qt5 syntax is used to create connections because old syntax does not work with multiple arguments for some unresolved reason. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented basic infrastructure to handle exceptions.Pavel Pisa2019-02-07
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Remove dependency of ALU operation encoding on MIPS instruction format.Pavel Pisa2019-02-07
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented base for exception handling.Pavel Pisa2019-02-06
| | | | | | | | | | | | | | Memory stage is chosen to be exception commit stage. Instructions flow postponed and stages holding following instructions are cleaned. Processing of syscall at decode stage as jump to the handler would be better solution in real hardware but for future emulated syscalls it is better to reach consistent state of registers. Memory access caused exceptions would require cleanup even in real hardware. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Resolve some memory leaks found by Valgrind.Pavel Pisa2019-02-06
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Reorganize PC handling and implement full REGIMM decode.Pavel Pisa2019-02-05
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct shift operation and make ALU_OP_MOVZ and ALU_OP_MOVN encoding ↵Pavel Pisa2019-02-05
| | | | | | independent. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Rewrite instruction decoding to be generic and mostly architecture independent.Pavel Pisa2019-02-05
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Remove almost all direct access to opcode and function from the core.Pavel Pisa2019-02-04
| | | | | | | Remaining are MOVZ and MOVN in the execution phase and all branch and jump operations in handle_pc(). Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Take into account actual requirements for rs, rt and rd write for individual ↵Pavel Pisa2019-02-04
| | | | | | instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Unified instructions table and access type move to machinedefs.h .Pavel Pisa2019-02-04
| | | | | | | This allows to specify requirement for RS and RD on instruction basis even for T_R / ALU instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Primitive implementation of cache instruction.Pavel Pisa2019-02-04
| | | | | | | When any variant of cache instruction is detected flush and invalidate whole data cache. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add license to the source files.Pavel Pisa2019-02-04
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement BREAK instruction to stop continuous execution.Pavel Pisa2019-02-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement instructions MULT, MULTU, DIV, DIVU.Pavel Pisa2019-02-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ ↵Pavel Pisa2019-02-02
| | | | | | | | | | | instructions. The previous code worked by chance only because decode has been fully processed including forwarding from M and W before PC processing started. But in real hardware the PC processing runs in parallel with ALU and cannot read its results in the same cycle. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Include support for JALR support.Pavel Pisa2019-01-31
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Initial support for JAL.Pavel Pisa2019-01-31
| | | | | | | The JR, BEQ, BNE are most probably incorrect still. There is missing forwarding for pipelined execution. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Display rs, rt, rd and write register number in all stages.Pavel Pisa2019-01-31
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct processing of ORI, ANDI, XORI instructions which require ↵Pavel Pisa2019-01-31
| | | | | | zero-extended immediate. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Do not replace rt by forward if instruction in T_R or store.Pavel Pisa2019-01-30
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Display execution stage forward signals in the view.Pavel Pisa2019-01-30
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct hazards processing.Pavel Pisa2019-01-30
| | | | | | | | The shorter loop has priority. This is achieved by later processing when it replaces possible result from longer loop over W stage. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add few more labelsKarel Kočí2018-05-24
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* Add buses statis viewsKarel Kočí2018-05-24
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* Fix load and store instructionsKarel Kočí2018-05-02
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* Implement LUIKarel Kočí2018-04-08
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* Implement sync for memoryKarel Kočí2018-04-08
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* Integrate cache with rest of the machine coreKarel Kočí2018-04-08
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* Fix forwarding checker for I and J and S* instructionsKarel Kočí2018-03-06
| | | | THere are exceptions when we care about forwarding and when we don't.
* Forward from execute stage to decode stage latchKarel Kočí2018-02-14
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* Do empty fetch stage to report fetch even if we stallKarel Kočí2018-02-14
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* Fix signextend in coreKarel Kočí2018-02-14
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* Add instruction view to single coreKarel Kočí2018-01-21
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* Cleanup some todos in codeKarel Kočí2018-01-15
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* Implement hazard unitKarel Kočí2018-01-15
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* Allow instruction trace from any stageKarel Kočí2018-01-11
| | | | | | In reality this internally allows us to see stages even it we are not using pipelining but that is hidden from outside simply to not confuse user.
* Implement machine restartKarel Kočí2018-01-05
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* Allow delay slot disable for non-pipelined coreKarel Kočí2018-01-03
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* Add trace-feth to qtmips_cliKarel Kočí2018-01-03
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* Put qtmips_machine to machine namespaceKarel Kočí2017-12-17
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* Implement some store and load instructionsKarel Kočí2017-12-12
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* Fix immediate alu operationKarel Kočí2017-12-12
| | | | | There should be a sign extension to 32bit when doing immediate operations.
* Implement branch and jump instructionsKarel Kočí2017-12-12
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