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path: root/qtmips_machine/cache.cpp
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* Implement LRU as simple priority queue with linear insert sort.Pavel Pisa2019-02-12
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add debug access to rword and friends to allow read data through cache ↵Pavel Pisa2019-02-12
| | | | | | | | without disturbing statistic. This allows to switch view between CPU and raw memory content. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Move computation of cache row, column and tag to single inline function.Pavel Pisa2019-02-08
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct cache LocationStatus when cache is disabled.Pavel Pisa2019-02-07
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented simple indication of presence of memory location in the cache.Pavel Pisa2019-02-07
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Added method to retrieve memory location status.Pavel Pisa2019-02-07
| | | | | | | It can inform if given location is cached or if given range is invalid in address space. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Resolve some memory leaks found by Valgrind.Pavel Pisa2019-02-06
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement simple address-space ranges registration and example peripheral.Pavel Pisa2019-02-06
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Define uncached region in range from 0xf0000000 to 0xffffffff.Pavel Pisa2019-02-04
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add license to the source files.Pavel Pisa2019-02-04
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct write-back cache behavior.Pavel Pisa2019-02-04
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct memory view updates for uncached and write-through case.Pavel Pisa2019-02-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add cache statisticsKarel Kočí2018-05-23
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* Initial implementation of cache viewKarel Kočí2018-04-17
| | | | It needs some more work to look nice but it already works.
* Show cache statistics in Memory block in coreviewKarel Kočí2018-04-15
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* Implement sync for memoryKarel Kočí2018-04-08
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* Integrate cache with rest of the machine coreKarel Kočí2018-04-08
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* Add associative cacheKarel Kočí2018-04-08
| | | | Not fully tested yet.
* Add initial implementatio of cachesKarel Kočí2018-04-07
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* Put qtmips_machine to machine namespaceKarel Kočí2017-12-17
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* Initial commitKarel Kočí2017-08-30
Adding work done so far.