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authorKarel Kočí <cynerd@email.cz>2018-04-08 11:55:52 +0200
committerKarel Kočí <cynerd@email.cz>2018-04-08 11:55:52 +0200
commit15dbd208fa6c1ac4dc0684c95c43cc40b2462cbf (patch)
treec360138011f0312860356ba1ff95387cb468588d /qtmips_machine/cache.cpp
parent3652d0a13857b7c341fb08a882e12c0b2205c8c0 (diff)
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Integrate cache with rest of the machine core
Diffstat (limited to 'qtmips_machine/cache.cpp')
-rw-r--r--qtmips_machine/cache.cpp32
1 files changed, 25 insertions, 7 deletions
diff --git a/qtmips_machine/cache.cpp b/qtmips_machine/cache.cpp
index f37db38..7432119 100644
--- a/qtmips_machine/cache.cpp
+++ b/qtmips_machine/cache.cpp
@@ -2,8 +2,15 @@
using namespace machine;
-Cache::Cache(Memory *m, MachineConfigCache *cc) : cnf(cc) {
+Cache::Cache(Memory *m, const MachineConfigCache *cc) : cnf(cc) {
mem = m;
+ // Zero hit and miss rate
+ hitc = 0;
+ missc = 0;
+ // Skip any other initialization if cache is disabled
+ if (!cc->enabled())
+ return;
+
// Allocate cache data structure
dt = new struct cache_data*[cc->associativity()];
for (unsigned i = 0; i < cc->associativity(); i++) {
@@ -27,12 +34,14 @@ Cache::Cache(Memory *m, MachineConfigCache *cc) : cnf(cc) {
default:
break;
}
- // Zero hit and miss rate
- hitc = 0;
- missc = 0;
}
void Cache::wword(std::uint32_t address, std::uint32_t value) {
+ if (!cnf.enabled()) {
+ mem->write_word(address, value);
+ return;
+ }
+
std::uint32_t *data;
access(address, &data, false);
*data = value;
@@ -42,27 +51,36 @@ void Cache::wword(std::uint32_t address, std::uint32_t value) {
}
std::uint32_t Cache::rword(std::uint32_t address) const {
+ if (!cnf.enabled())
+ return mem->read_word(address);
+
std::uint32_t *data;
access(address, &data, true);
return *data;
}
void Cache::flush() {
+ if (!cnf.enabled())
+ return;
+
for (unsigned as = 0; as < cnf.associativity(); as++)
for (unsigned st = 0; st < cnf.sets(); st++)
if (dt[as][st].valid)
kick(as, st);
}
-unsigned Cache::hit() {
+unsigned Cache::hit() const {
return hitc;
}
-unsigned Cache::miss() {
+unsigned Cache::miss() const {
return missc;
}
void Cache::reset() {
+ if (!cnf.enabled())
+ return;
+
// Set all cells to ne invalid
for (unsigned as = 0; as < cnf.associativity(); as++)
for (unsigned st = 0; st < cnf.sets(); st++)
@@ -73,7 +91,7 @@ void Cache::reset() {
missc = 0;
}
-const MachineConfigCache &Cache::config() {
+const MachineConfigCache &Cache::config() const {
return cnf;
}