| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | Ensure that cache view and memory status are updated after cache flush. | Pavel Pisa | 2019-02-21 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Add burst time and store timing in the config. | Pavel Pisa | 2019-02-21 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Distinguish between write-through cache with allocate and update only if hit. | Pavel Pisa | 2019-02-20 |
| | | | | | | | | Add into cache statistic number of backing/main memory accesses. Correction of meaning and computation of the cache statistic. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Clear LFU statistic for the kicked out cache-line. | Pavel Pisa | 2019-02-18 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement LRU as simple priority queue with linear insert sort. | Pavel Pisa | 2019-02-12 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Add debug access to rword and friends to allow read data through cache ↵ | Pavel Pisa | 2019-02-12 |
| | | | | | | | | | without disturbing statistic. This allows to switch view between CPU and raw memory content. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Move computation of cache row, column and tag to single inline function. | Pavel Pisa | 2019-02-08 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct cache LocationStatus when cache is disabled. | Pavel Pisa | 2019-02-07 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implemented simple indication of presence of memory location in the cache. | Pavel Pisa | 2019-02-07 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Added method to retrieve memory location status. | Pavel Pisa | 2019-02-07 |
| | | | | | | | | It can inform if given location is cached or if given range is invalid in address space. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Resolve some memory leaks found by Valgrind. | Pavel Pisa | 2019-02-06 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement simple address-space ranges registration and example peripheral. | Pavel Pisa | 2019-02-06 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Define uncached region in range from 0xf0000000 to 0xffffffff. | Pavel Pisa | 2019-02-04 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Add license to the source files. | Pavel Pisa | 2019-02-04 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct write-back cache behavior. | Pavel Pisa | 2019-02-04 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct memory view updates for uncached and write-through case. | Pavel Pisa | 2019-02-03 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Add cache statistics | Karel Kočí | 2018-05-23 |
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| * | Initial implementation of cache view | Karel Kočí | 2018-04-17 |
| | | | | | It needs some more work to look nice but it already works. | ||
| * | Show cache statistics in Memory block in coreview | Karel Kočí | 2018-04-15 |
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| * | Implement sync for memory | Karel Kočí | 2018-04-08 |
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| * | Integrate cache with rest of the machine core | Karel Kočí | 2018-04-08 |
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| * | Add associative cache | Karel Kočí | 2018-04-08 |
| | | | | | Not fully tested yet. | ||
| * | Add initial implementatio of caches | Karel Kočí | 2018-04-07 |
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| * | Put qtmips_machine to machine namespace | Karel Kočí | 2017-12-17 |
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| * | Initial commit | Karel Kočí | 2017-08-30 |
| Adding work done so far. | |||
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index : qtmips | |
| MIPS CPU emulator for education purposes | Gitolite user |
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