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* Suppress warning where case fall-through is intentional.Pavel Pisa2019-03-06
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct parsing of register + offset operands, i.e., LW and SW.Pavel Pisa2019-03-06
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Include description of partial coprocessor 0 support in README.Pavel Pisa2019-03-05
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Try the strict check of encoded instructions and relax break and other.Pavel Pisa2019-03-05
| | | | | | | Some instructions can have fields to be used by operating system or for error reporting by user. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Complete revamp of disassembler and assembler arguments processing.Pavel Pisa2019-03-05
| | | | | | | | | | | | | | | | | | | | | Instructions description in instruction.cpp has been pragmatically augmented by tool based on Python MIPS simulator, hazards analyzer https://github.com/ppisa/apo-simarch That code has been originally distilled from from GNU binutils sources. Implementation is now inline with my original proposal Previous solution gets untenable with more complex instructions and its complexity would grow extremely. MIPS instruction set with coprocessor instructions which use sel field, rd used as index, rt as destination and other peculiarities in newer versions cannot be processed based on basic CPU control signals. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Dock to view coprocessor 0 and cop0 counter/comparator support.Pavel Pisa2019-03-05
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Use irq 3 (HW1) for Rx and irq 2 (HW0) for Tx to be compatible with SPIM.Pavel Pisa2019-03-04
| | | | | | | Jump to address 0x8000180 by default and to EBase + 0x180 when EBase is set to be compatible with real MIPS CPU. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented interrupt delivery and processing for serial port.Pavel Pisa2019-03-04
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented coprocessor 0 registers access and register EPC and Cause set by ↵Pavel Pisa2019-03-04
| | | | | | exception. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* build.sh: use -recursive instead of explicit listKarel Kočí2019-03-02
| | | | Signed-off-by: Karel Kočí <cynerd@email.cz>
* Add dependency of qtmips_gui on qtmips_osemu.Pavel Pisa2019-03-02
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Simple serial port receive implementation.Pavel Pisa2019-02-25
| | | | | | | | | Simple polled mode serial port input implemented for serial port peripheral and for read and readv system calls. When end of input character reserve is reached for read/readv, newline is automatically appended. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Exceptions causes align with SPIM and add serial port range alias equivalent ↵Pavel Pisa2019-02-25
| | | | | | to SPIM. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Change serial port peripheral to match SPIM registers definition.Pavel Pisa2019-02-25
| | | | | | | Still Tx only and keep 0xffffc000 base to allows single instruction LW and SW access. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct relative jumps range and adjust it for single core without delay-slot.Pavel Pisa2019-02-24
| | | | | | | | | | | | Setting bits 16 to 31 to 1 is incorrect, offset is shift by two so bit 16 can be zero for jumps in range -64k to -128k. Adjust relative offsets to compute target address same, as if there is delay slot, for CPU variant without delay slot. This allows to use same/standard MIPS assembler for mode without delay slots. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* README - update list of supported instructions.Pavel Pisa2019-02-24
| | | | | | | Complete list from MIPS32 Instruction Set Quick Reference is supported now. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement ROTR and ROTRV and full decode of WSBH, SEB and SEH.Pavel Pisa2019-02-24
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add some more labels and clarify rs, rt, rd in execute stage.Pavel Pisa2019-02-24
| | | | | | | This allows simple visual compare of rs and rt in execution stage with register number to be written in memory and write-back stages. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add action to show symbols into pull down menu.Pavel Pisa2019-02-22
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add support for goto to selected symbol address.Pavel Pisa2019-02-22
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Ensure that cache view and memory status are updated after cache flush.Pavel Pisa2019-02-21
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Added test for LWR, LWL, SWR and SWL instructions.Pavel Pisa2019-02-21
| | | | | | | The reference data has been obtained by running application under userspace MIPS QEMU. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add burst time and store timing in the config.Pavel Pisa2019-02-21
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Adjust label of PC to R31 and add jump to reg.Pavel Pisa2019-02-20
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Distinguish between write-through cache with allocate and update only if hit.Pavel Pisa2019-02-20
| | | | | | | Add into cache statistic number of backing/main memory accesses. Correction of meaning and computation of the cache statistic. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Update project files to adapt for release and debug libraries location for ↵Pavel Pisa2019-02-19
| | | | | | Windows builds. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Update MultiText to use setPointSize too.Pavel Pisa2019-02-19
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* pointSize -> pixelSizeFanda Vacek2019-02-19
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* variable font sizeFanda Vacek2019-02-19
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* The sizeHint seems to not be affected by invisible zero size problem.Pavel Pisa2019-02-19
| | | | | | | | Enable number of columns computation even for invisible QLabels to restore wide registers dock with multiple columns instead of only one. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Clear LFU statistic for the kicked out cache-line.Pavel Pisa2019-02-18
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add unlimited checkbox to the tool-bar.Pavel Pisa2019-02-18
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Report forward and stall for branches and add forward to execution phase.Pavel Pisa2019-02-18
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct ADD operation to map to ALU variant with overflow checking.Pavel Pisa2019-02-18
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Visualize request to stall and stall in execution phase and exception sources.Pavel Pisa2019-02-18
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Stall the pipeline even for branch which requires memory read as argument.Pavel Pisa2019-02-18
| | | | | | | | | | This type of the hazard doe not cause problems in the simulator because processing of memory stage is already finished at time when PC handling is started but it would cause problems in real hardware where PC handling is processed in parallel to memory load. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Update homepage to point to CVUT GitHub repository.Pavel Pisa2019-02-18
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Do not update instruction in the decode stage when stalled.Pavel Pisa2019-02-17
| | | | | | | Decode dt_d represents next input to execute stage not state of decode stage at this moment. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* docs: more clarification how to use compillersPavel Pisa2019-02-17
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* docs: startup code for both PIC and non-PIC environments.Pavel Pisa2019-02-17
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* Ignore LWC1, LWD1, SWC1 and SDC1 instructions.Pavel Pisa2019-02-17
| | | | | | This allows to use MUSL Lib C printf and scanf implementations. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Pass arithmetic exception trough pipeline and implement trap support and ↵Pavel Pisa2019-02-17
| | | | | | instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Change RGB LEDs signals and slots to unsigned value.Pavel Pisa2019-02-16
| | | | | | | Signed value caused in the conversion incorrect behavior for some corner cases. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct final loop label in documentation.Pavel Pisa2019-02-16
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* Enable copy from memory and program views.Pavel Pisa2019-02-15
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* System calls stubs for brk and mmap2.Pavel Pisa2019-02-15
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Multiply and accumulate and CLZ/CLO operations added.Pavel Pisa2019-02-15
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement EXT instruction used in GLIBC startup.Pavel Pisa2019-02-15
| | | | | | It requires one more field to pass to ALU. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Core: move complex memory operation to own function and implement LWL, LWR, ↵Pavel Pisa2019-02-15
| | | | | | | | SWL, SWR. The move makes basic memory stage processing more readable. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Fill the rest of ALU opcode table to file all 64 entries.Pavel Pisa2019-02-14
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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