| Commit message (Collapse) | Author | Age |
... | |
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
|
| |
Some instructions can have fields to be used by operating system
or for error reporting by user.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Instructions description in instruction.cpp has been
pragmatically augmented by tool based on Python MIPS simulator,
hazards analyzer
https://github.com/ppisa/apo-simarch
That code has been originally distilled from from GNU
binutils sources.
Implementation is now inline with my original proposal
Previous solution gets untenable with more complex
instructions and its complexity would grow extremely.
MIPS instruction set with coprocessor instructions
which use sel field, rd used as index, rt as destination
and other peculiarities in newer versions cannot
be processed based on basic CPU control signals.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
|
| |
Jump to address 0x8000180 by default and to EBase + 0x180
when EBase is set to be compatible with real MIPS CPU.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
| |
exception.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Karel Kočí <cynerd@email.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
|
|
|
| |
Simple polled mode serial port input implemented for
serial port peripheral and for read and readv system
calls. When end of input character reserve is reached
for read/readv, newline is automatically appended.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
| |
to SPIM.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
|
| |
Still Tx only and keep 0xffffc000 base to allows single
instruction LW and SW access.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Setting bits 16 to 31 to 1 is incorrect, offset is shift
by two so bit 16 can be zero for jumps in range -64k to -128k.
Adjust relative offsets to compute target address same, as if there
is delay slot, for CPU variant without delay slot.
This allows to use same/standard MIPS assembler for mode
without delay slots.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
|
| |
Complete list from MIPS32 Instruction Set Quick Reference
is supported now.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
|
| |
This allows simple visual compare of rs and rt in execution stage
with register number to be written in memory and write-back stages.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
|
| |
The reference data has been obtained by running application
under userspace MIPS QEMU.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
|
| |
Add into cache statistic number of backing/main memory accesses.
Correction of meaning and computation of the cache statistic.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
| |
Windows builds.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
| |
|
| |
|
|
|
|
|
|
|
|
| |
Enable number of columns computation even for invisible QLabels
to restore wide registers dock with multiple columns instead
of only one.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
|
|
|
|
| |
This type of the hazard doe not cause problems in the simulator
because processing of memory stage is already finished
at time when PC handling is started but it would cause
problems in real hardware where PC handling is processed
in parallel to memory load.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
|
| |
Decode dt_d represents next input to execute stage
not state of decode stage at this moment.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
| |
|
| |
|
|
|
|
|
|
| |
This allows to use MUSL Lib C printf and scanf implementations.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
| |
instructions.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
|
| |
Signed value caused in the conversion incorrect behavior
for some corner cases.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
| |
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
| |
It requires one more field to pass to ALU.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
|
|
| |
SWL, SWR.
The move makes basic memory stage processing more readable.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
| |
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|