aboutsummaryrefslogtreecommitdiff
path: root/qtmips_machine
diff options
context:
space:
mode:
Diffstat (limited to 'qtmips_machine')
-rw-r--r--qtmips_machine/machineconfig.cpp14
-rw-r--r--qtmips_machine/machineconfig.h6
2 files changed, 10 insertions, 10 deletions
diff --git a/qtmips_machine/machineconfig.cpp b/qtmips_machine/machineconfig.cpp
index ce0e3d8..13a1ff2 100644
--- a/qtmips_machine/machineconfig.cpp
+++ b/qtmips_machine/machineconfig.cpp
@@ -64,17 +64,17 @@ void MachineConfigCache::store(QSettings *sts, const QString &prefix) {
void MachineConfigCache::preset(enum ConfigPresets p) {
switch (p) {
- case CP_PIPE_CACHE:
+ case CP_PIPE:
+ case CP_SINGLE_CACHE:
set_enabled(true);
- set_sets(3);
- set_blocks(1);
- set_associativity(1);
+ set_sets(4);
+ set_blocks(2);
+ set_associativity(2);
set_replacement_policy(RP_RAND);
set_write_policy(WP_TROUGH);
break;
case CP_SINGLE:
case CP_PIPE_NO_HAZARD:
- case CP_PIPE_NO_CACHE:
set_enabled(false);
}
}
@@ -198,6 +198,7 @@ void MachineConfig::preset(enum ConfigPresets p) {
// Note: we set just a minimal subset to get preset (preserving as much of hidden configuration as possible)
switch (p) {
case CP_SINGLE:
+ case CP_SINGLE_CACHE:
set_pipelined(false);
set_delay_slot(true);
break;
@@ -205,8 +206,7 @@ void MachineConfig::preset(enum ConfigPresets p) {
set_pipelined(true);
set_hazard_unit(MachineConfig::HU_NONE);
break;
- case CP_PIPE_CACHE:
- case CP_PIPE_NO_CACHE:
+ case CP_PIPE:
set_pipelined(true);
set_hazard_unit(MachineConfig::HU_STALL_FORWARD);
break;
diff --git a/qtmips_machine/machineconfig.h b/qtmips_machine/machineconfig.h
index 1ec2703..56cdf8e 100644
--- a/qtmips_machine/machineconfig.h
+++ b/qtmips_machine/machineconfig.h
@@ -8,9 +8,9 @@ namespace machine {
enum ConfigPresets {
CP_SINGLE, // No pipeline cpu without cache
- CP_PIPE_NO_HAZARD, // Pipelined cpu without hazard unit
- CP_PIPE_NO_CACHE, // Pipelined cpu without cache
- CP_PIPE_CACHE // Full pipelined cpu
+ CP_SINGLE_CACHE, // No pipeline cpu with cache
+ CP_PIPE_NO_HAZARD, // Pipelined cpu without hazard unit and without cache
+ CP_PIPE // Full pipelined cpu
};
class MachineConfigCache {