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-rw-r--r--qtmips_machine/alu.cpp6
-rw-r--r--qtmips_machine/alu.h2
-rw-r--r--qtmips_machine/core.cpp8
-rw-r--r--qtmips_machine/tests/testalu.cpp14
-rw-r--r--qtmips_machine/tests/testcore.cpp16
5 files changed, 45 insertions, 1 deletions
diff --git a/qtmips_machine/alu.cpp b/qtmips_machine/alu.cpp
index 07e174e..8be9f2a 100644
--- a/qtmips_machine/alu.cpp
+++ b/qtmips_machine/alu.cpp
@@ -17,6 +17,12 @@ std::uint32_t alu_operate(enum AluOp operation, std::uint32_t s, std::uint32_t t
case ALU_OP_SRAV:
// TODO is this correct implementation? (Should we be masking top most bit?)
return ((t & 0x7fffffff) >> s) | (t & 0x80000000);
+ case ALU_OP_MOVZ:
+ // We do this just to implement valid alu operation but we have to evaluate comparison way before this to disable register write
+ return t == 0 ? s : 0;
+ case ALU_OP_MOVN:
+ // Same note as for MOVZ applies here
+ return t != 0 ? s : 0;
case ALU_OP_MFHI:
return regs->read_hi_lo(true);
case ALU_OP_MTHI:
diff --git a/qtmips_machine/alu.h b/qtmips_machine/alu.h
index 2c311d2..4818bb1 100644
--- a/qtmips_machine/alu.h
+++ b/qtmips_machine/alu.h
@@ -14,6 +14,8 @@ enum AluOp : std::uint8_t {
ALU_OP_SLLV,
ALU_OP_SRLV = 6,
ALU_OP_SRAV,
+ ALU_OP_MOVZ = 10,
+ ALU_OP_MOVN,
ALU_OP_MFHI = 16,
ALU_OP_MTHI,
ALU_OP_MFLO,
diff --git a/qtmips_machine/core.cpp b/qtmips_machine/core.cpp
index 1008886..20c1b74 100644
--- a/qtmips_machine/core.cpp
+++ b/qtmips_machine/core.cpp
@@ -126,8 +126,14 @@ struct Core::dtDecode Core::decode(struct dtFetch dt) {
struct Core::dtExecute Core::execute(struct dtDecode dt) {
// TODO signals
+ // Handle conditional move (we have to change regwrite signal if conditional is not met)
+ // TODO can't we do this some cleaner way?
+ bool regwrite = dt.regwrite;
+ if (dt.inst.opcode() == 0 && ((dt.inst.funct() == 10 && dt.val_rt != 0) || (dt.inst.funct() == 11 && dt.val_rt == 0)))
+ regwrite = false;
+
return {
- .regwrite = dt.regwrite,
+ .regwrite = regwrite,
.rwrite = dt.regd ? dt.inst.rd() : dt.inst.rt(),
.alu_val = alu_operate(dt.aluop, dt.val_rs, dt.alusrc ? dt.inst.immediate() : dt.val_rt, dt.inst.shamt(), regs),
};
diff --git a/qtmips_machine/tests/testalu.cpp b/qtmips_machine/tests/testalu.cpp
index b45a317..603a610 100644
--- a/qtmips_machine/tests/testalu.cpp
+++ b/qtmips_machine/tests/testalu.cpp
@@ -12,6 +12,20 @@ void MachineTests::alu_data() {
QTest::addColumn<std::uint32_t>("res");
// TODO SLL-SRAV
+ QTest::newRow("MOVZ") << ALU_OP_MOVZ \
+ << (std::uint32_t)22 \
+ << (std::uint32_t)0 \
+ << (std::uint8_t)0 \
+ << Registers() \
+ << Registers() \
+ << (std::uint32_t)22;
+ QTest::newRow("MOVN") << ALU_OP_MOVN \
+ << (std::uint32_t)22 \
+ << (std::uint32_t)1 \
+ << (std::uint8_t)0 \
+ << Registers() \
+ << Registers() \
+ << (std::uint32_t)22;
{
Registers init;
init.write_hi_lo(true, 42);
diff --git a/qtmips_machine/tests/testcore.cpp b/qtmips_machine/tests/testcore.cpp
index 835dd2c..27a49b4 100644
--- a/qtmips_machine/tests/testcore.cpp
+++ b/qtmips_machine/tests/testcore.cpp
@@ -127,6 +127,8 @@ static void core_regs_data() {
Registers regs_init;
regs_init.write_hi_lo(true, 24);
regs_init.write_hi_lo(false, 28);
+ regs_init.write_gp(24, 55);
+ regs_init.write_gp(25, 56);
regs_init.write_gp(27, 21);
regs_init.write_gp(28, 22);
Registers regs_res(regs_init);
@@ -148,6 +150,20 @@ static void core_regs_data() {
QTest::newRow("MTLO") << Instruction(0, 28, 0, 0, 0, 19) \
<< regs_init \
<< regs_res;
+ regs_res.write_hi_lo(false, 28);
+ QTest::newRow("MOVZ-F") << Instruction(0, 24, 24, 25, 0, 10) \
+ << regs_init \
+ << regs_res;
+ QTest::newRow("MOVN-F") << Instruction(0, 24, 1, 25, 0, 11) \
+ << regs_init \
+ << regs_res;
+ regs_res.write_gp(25, 55);
+ QTest::newRow("MOVZ-T") << Instruction(0, 24, 1, 25, 0, 10) \
+ << regs_init \
+ << regs_res;
+ QTest::newRow("MOVN-T") << Instruction(0, 24, 24, 25, 0, 11) \
+ << regs_init \
+ << regs_res;
}
}