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-rw-r--r--qtmips_machine/instruction.cpp8
-rw-r--r--qtmips_machine/instruction.h50
2 files changed, 30 insertions, 28 deletions
diff --git a/qtmips_machine/instruction.cpp b/qtmips_machine/instruction.cpp
index 3fb8839..694a32d 100644
--- a/qtmips_machine/instruction.cpp
+++ b/qtmips_machine/instruction.cpp
@@ -47,7 +47,7 @@ using namespace machine;
#define FLAGS_ALU_I_LOAD (IMF_SUPPORTED | IMF_ALUSRC | IMF_REGWRITE | \
IMF_MEMREAD | IMF_MEM | IMF_ALU_REQ_RS)
#define FLAGS_ALU_I_STORE (IMF_SUPPORTED | IMF_ALUSRC | IMF_MEMWRITE | \
- IMF_MEM | IMF_MEM_STORE | IMF_ALU_REQ_RS | IMF_ALU_REQ_RT)
+ IMF_MEM | IMF_ALU_REQ_RS | IMF_ALU_REQ_RT)
#define FLAGS_ALU_T_R_D (IMF_SUPPORTED | IMF_REGD | IMF_REGWRITE)
#define FLAGS_ALU_T_R_STD (FLAGS_ALU_T_R_D | IMF_ALU_REQ_RS | IMF_ALU_REQ_RT)
@@ -356,15 +356,15 @@ static const struct InstructionMap instruction_map[] = {
{"SH", IT_I, ALU_OP_ADDU, AC_HALFWORD, nullptr, // SH
.flags = FLAGS_ALU_I_STORE},
{"SWL", IT_I, ALU_OP_ADDU, NOMEM, nullptr, // SWL
- .flags = IMF_MEM | IMF_MEM_STORE},
+ .flags = IMF_MEM | IMF_MEMWRITE},
{"SW", IT_I, ALU_OP_ADDU, AC_WORD, nullptr, // SW
.flags = FLAGS_ALU_I_STORE},
IM_UNKNOWN, // 44
IM_UNKNOWN, // 45
{"SWR", IT_I, ALU_OP_ADDU, NOMEM, nullptr, // SWR
- .flags = IMF_MEM | IMF_MEM_STORE},
+ .flags = IMF_MEM | IMF_MEMWRITE},
{"CACHE", IT_I, ALU_OP_ADDU, AC_CACHE_OP, nullptr, // CACHE
- .flags = IMF_SUPPORTED | IMF_ALUSRC | IMF_MEM| IMF_MEM_STORE},
+ .flags = IMF_SUPPORTED | IMF_ALUSRC | IMF_MEM},
{"LL", IT_I, ALU_OP_ADDU, AC_LOAD_LINKED, nullptr, // LL
.flags = FLAGS_ALU_I_LOAD},
IM_UNKNOWN, // 49
diff --git a/qtmips_machine/instruction.h b/qtmips_machine/instruction.h
index d8b9d00..bb6f410 100644
--- a/qtmips_machine/instruction.h
+++ b/qtmips_machine/instruction.h
@@ -45,30 +45,32 @@ namespace machine {
enum InstructionFlags {
IMF_NONE = 0,
- IMF_SUPPORTED = 1L<<0,
- IMF_MEMWRITE = 1L<<1,
- IMF_MEMREAD = 1L<<2,
- IMF_ALUSRC = 1L<<3,
- IMF_REGD = 1L<<4,
- IMF_REGWRITE = 1L<<5,
- IMF_ZERO_EXTEND= 1L<<6,
- IMF_PC_TO_R31 = 1L<<7,
- IMF_BJR_REQ_RS = 1L<<8,
- IMF_BJR_REQ_RT = 1L<<9,
- IMF_ALU_SHIFT = 1L<<10,
- IMF_MEM = 1L<<11, // This instruction is memory access instruction,
- IMF_MEM_STORE = 1L<<12,
- IMF_ALU_REQ_RS = 1L<<13,
- IMF_ALU_REQ_RT = 1L<<14,
- IMF_READ_HILO = 1L<<15,
- IMF_WRITE_HILO = 1L<<16,
- IMF_PC8_TO_RT = 1L<<17,
- IMF_BRANCH = 1L<<18,
- IMF_JUMP = 1L<<19,
- IMF_BJ_NOT = 1L<<20,
- IMF_BGTZ_BLEZ = 1L<<21,
- IMF_NB_SKIP_DS = 1L<<22, // Skip instruction in delay slot if branch not taken
- IMF_EXCEPTION = 1L<<23,
+ IMF_SUPPORTED = 1L<<0, /**< Instruction is supported */
+ IMF_MEMWRITE = 1L<<1, /**< Write to the memory when memory stage is reached */
+ IMF_MEMREAD = 1L<<2, /**< Read from the memory when memory stage is reached */
+ IMF_ALUSRC = 1L<<3, /**< The second ALU source is immediate operand */
+ IMF_REGD = 1L<<4, /**< RD field specifies register to be updated, if not
+ set and REGWRITE = 1, then destination reg in RT */
+ IMF_REGWRITE = 1L<<5, /**< Instruction result (ALU or memory) is written to
+ register file */
+ IMF_ZERO_EXTEND= 1L<<6, /**< Immediate operand is zero extended, else sign */
+ IMF_PC_TO_R31 = 1L<<7, /**< PC value will be stored to register R31/RA */
+ IMF_BJR_REQ_RS = 1L<<8, /**< Branch or jump operation reguires RS value */
+ IMF_BJR_REQ_RT = 1L<<9, /**< Branch or jump operation requires RT value */
+ IMF_ALU_SHIFT = 1L<<10, /**< Operation is shift of RT by RS or SHAMT */
+ IMF_MEM = 1L<<11, /**< Instruction is memory access instruction */
+ IMF_ALU_REQ_RS = 1L<<12, /**< Execution phase/ALU requires RS value */
+ IMF_ALU_REQ_RT = 1L<<13, /**< Execution phase/ALU/mem requires RT value */
+ IMF_READ_HILO = 1L<<14, /**< Operation reads value from HI or LO registers */
+ IMF_WRITE_HILO = 1L<<15, /**< Operation writes value to HI and/or LO registers */
+ IMF_PC8_TO_RT = 1L<<16, /**< PC value will be stored in RT specified register */
+ IMF_BRANCH = 1L<<17, /**< Operation is conditional or unconditional branch
+ or branch and link when PC_TO_R31 is set */
+ IMF_JUMP = 1L<<18, /**< Jump operation - J, JAL, JR or JALR */
+ IMF_BJ_NOT = 1L<<19, /**< Negate condition for branch instructiion */
+ IMF_BGTZ_BLEZ = 1L<<20, /**< BGTZ/BLEZ, else BEGT/BLTZ or BEQ, BNE when RT */
+ IMF_NB_SKIP_DS = 1L<<21, /**< Skip instruction in delay slot if branch not taken */
+ IMF_EXCEPTION = 1L<<22, /**< Instruction causes synchronous exception */
};
class Instruction {