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-rw-r--r--qtmips_machine/core.cpp31
-rw-r--r--qtmips_machine/instruction.cpp15
-rw-r--r--qtmips_machine/instruction.h3
3 files changed, 9 insertions, 40 deletions
diff --git a/qtmips_machine/core.cpp b/qtmips_machine/core.cpp
index d91a36e..4edf35a 100644
--- a/qtmips_machine/core.cpp
+++ b/qtmips_machine/core.cpp
@@ -89,33 +89,8 @@ struct Core::dtDecode Core::decode(const struct dtFetch &dt) {
// requires rs for beq, bne, blez, bgtz, jr nad jalr
bool bjr_req_rs = flags & IMF_BJR_REQ_RS;
- if (dt.inst.opcode() == 0) {
- switch (dt.inst.funct()) {
- case ALU_OP_BREAK:
- FALLTROUGH
- case ALU_OP_MTHI:
- FALLTROUGH
- case ALU_OP_MTLO:
- FALLTROUGH
- case ALU_OP_MULT:
- FALLTROUGH
- case ALU_OP_MULTU:
- FALLTROUGH
- case ALU_OP_DIV:
- FALLTROUGH
- case ALU_OP_DIVU:
- regwrite = false;
- break;
- case ALU_OP_JR:
- regwrite = false;
- bjr_req_rs = true;
- break;
- case ALU_OP_JALR:
- val_rt = dt.inst_addr + 8;
- bjr_req_rs = true;
- break;
- }
- }
+ if (flags & IMF_PC8_TO_RT)
+ val_rt = dt.inst_addr + 8;
// requires rt for beq, bne
bool bjr_req_rt = flags & IMF_BJR_REQ_RT;
@@ -159,7 +134,7 @@ struct Core::dtDecode Core::decode(const struct dtFetch &dt) {
.bjr_req_rt = bjr_req_rt,
.forward_m_d_rs = false,
.forward_m_d_rt = false,
- .aluop = dt.inst.opcode() == 0 ? (enum AluOp)dt.inst.funct() : alu_op,
+ .aluop = alu_op,
.memctl = mem_ctl,
.val_rs = val_rs,
.val_rt = val_rt,
diff --git a/qtmips_machine/instruction.cpp b/qtmips_machine/instruction.cpp
index 4c91d6f..c11e621 100644
--- a/qtmips_machine/instruction.cpp
+++ b/qtmips_machine/instruction.cpp
@@ -176,7 +176,7 @@ struct AluInstructionMap {
unsigned int flags;
};
-#define AIM_UNKNOWN {"UNKNOWN"}
+#define AIM_UNKNOWN {"UNKNOWN", IMF_NONE}
// This table is indexed by funct
static const struct AluInstructionMap alu_instruction_map[] = {
{"SLL", FLAGS_ALU_T_R_STD},
@@ -187,8 +187,8 @@ static const struct AluInstructionMap alu_instruction_map[] = {
AIM_UNKNOWN,
{"SRLV", FLAGS_ALU_T_R_STD},
{"SRAV", FLAGS_ALU_T_R_STD},
- {"JR", FLAGS_ALU_T_R_S},
- {"JALR", FLAGS_ALU_T_R_SD},
+ {"JR", IMF_SUPPORTED | IMF_BJR_REQ_RS},
+ {"JALR", IMF_SUPPORTED | IMF_REGD | IMF_REGWRITE | IMF_BJR_REQ_RS | IMF_PC8_TO_RT},
{"MOVZ", FLAGS_ALU_T_R_STD},
{"MOVN", FLAGS_ALU_T_R_STD},
AIM_UNKNOWN,
@@ -321,7 +321,7 @@ enum AluOp Instruction::alu_op() const {
if (opcode() >= (sizeof(instruction_map) / sizeof(struct InstructionMap)))
return ALU_OP_UNKNOWN;
const struct InstructionMap &im = instruction_map[opcode()];
- return im.alu;
+ return opcode() == 0? (enum AluOp)funct(): im.alu;
}
enum AccessControl Instruction::mem_ctl() const {
if (opcode() >= (sizeof(instruction_map) / sizeof(struct InstructionMap)))
@@ -330,13 +330,6 @@ enum AccessControl Instruction::mem_ctl() const {
return im.mem_ctl;
}
-bool Instruction::is_store() const {
- if (opcode() >= (sizeof(instruction_map) / sizeof(struct InstructionMap)))
- return false;
- const struct InstructionMap &im = instruction_map[opcode()];
- return im.flags & IMF_MEM_STORE;
-}
-
bool Instruction::is_break() const {
return opcode() == 0 && funct() == ALU_OP_BREAK;
}
diff --git a/qtmips_machine/instruction.h b/qtmips_machine/instruction.h
index 8286679..c19a205 100644
--- a/qtmips_machine/instruction.h
+++ b/qtmips_machine/instruction.h
@@ -44,6 +44,7 @@
namespace machine {
enum InstructionFlags {
+ IMF_NONE = 0,
IMF_SUPPORTED = 1L<<0,
IMF_MEMWRITE = 1L<<1,
IMF_MEMREAD = 1L<<2,
@@ -61,6 +62,7 @@ enum InstructionFlags {
IMF_ALU_REQ_RT = 1L<<14,
IMF_READ_HILO = 1L<<15,
IMF_WRITE_HILO = 1L<<16,
+ IMF_PC8_TO_RT = 1L<<17,
};
class Instruction {
@@ -93,7 +95,6 @@ public:
enum AluOp alu_op() const;
enum AccessControl mem_ctl() const;
- bool is_store() const; // Store instructions requires some additional handling so identify them
bool is_break() const;
bool operator==(const Instruction &c) const;