diff options
| -rw-r--r-- | qtmips_gui/coreview.cpp | 5 | ||||
| -rw-r--r-- | qtmips_machine/core.cpp | 14 | ||||
| -rw-r--r-- | qtmips_machine/core.h | 10 |
3 files changed, 29 insertions, 0 deletions
diff --git a/qtmips_gui/coreview.cpp b/qtmips_gui/coreview.cpp index f875ee8..0f10628 100644 --- a/qtmips_gui/coreview.cpp +++ b/qtmips_gui/coreview.cpp @@ -393,4 +393,9 @@ CoreViewScenePipelined::CoreViewScenePipelined(machine::QtMipsMachine *machine) NEW_V(360, 105, decode_regw_value, false, 1); NEW_V(460, 105, execute_regw_value, false, 1); NEW_V(560, 105, execute_regw_value, false, 1); + + if (machine->config().hazard_unit() == machine::MachineConfig::HU_STALL_FORWARD) { + NEW_V(448, 460, execute_reg1_ff_value, false, 1); // Register 1 forward + NEW_V(462, 460, execute_reg2_ff_value, false, 1); // Register 1 forward + } } diff --git a/qtmips_machine/core.cpp b/qtmips_machine/core.cpp index 5a0e831..17f2ccc 100644 --- a/qtmips_machine/core.cpp +++ b/qtmips_machine/core.cpp @@ -151,6 +151,8 @@ struct Core::dtDecode Core::decode(const struct dtFetch &dt) { .memctl = dec.mem_ctl, .val_rs = val_rs, .val_rt = val_rt, + .ff_rs = FORWARD_NONE, + .ff_rt = FORWARD_NONE, }; } @@ -171,6 +173,8 @@ struct Core::dtExecute Core::execute(const struct dtDecode &dt) { emit execute_alu_value(alu_val); emit execute_reg1_value(dt.val_rs); emit execute_reg2_value(dt.val_rt); + emit execute_reg1_ff_value(dt.ff_rs); + emit execute_reg2_ff_value(dt.ff_rt); emit execute_immediate_value(sign_extend(dt.inst.immediate())); emit execute_regw_value(dt.regwrite); emit execute_memtoreg_value(dt.memread); @@ -294,6 +298,8 @@ void Core::dtDecodeInit(struct dtDecode &dt) { dt.aluop = ALU_OP_SLL; dt.val_rs = 0; dt.val_rt = 0; + dt.ff_rs = FORWARD_NONE; + dt.ff_rt = FORWARD_NONE; } void Core::dtExecuteInit(struct dtExecute &dt) { @@ -361,6 +367,10 @@ void CorePipelined::do_step() { // TODO signals bool stall = false; + + dt_d.ff_rs = FORWARD_NONE; + dt_d.ff_rt = FORWARD_NONE; + if (hazard_unit != MachineConfig::HU_NONE) { // Note: We make exception with $0 as that has no effect when written and is used in nop instruction @@ -377,9 +387,11 @@ void CorePipelined::do_step() { // Forward result value if (dt_m.rwrite == dt_d.inst.rs()) { dt_d.val_rs = dt_m.towrite_val; + dt_d.ff_rs = FORWARD_FROM_M; } if (dt_m.rwrite == dt_d.inst.rt()) { dt_d.val_rt = dt_m.towrite_val; + dt_d.ff_rt = FORWARD_FROM_M; } } else stall = true; @@ -393,9 +405,11 @@ void CorePipelined::do_step() { // Forward result value if (dt_e.rwrite == dt_d.inst.rs()) { dt_d.val_rs = dt_e.alu_val; + dt_d.ff_rs = FORWARD_FROM_W; } if (dt_e.rwrite == dt_d.inst.rt()) { dt_d.val_rt = dt_e.alu_val; + dt_d.ff_rt = FORWARD_FROM_W; } } } else diff --git a/qtmips_machine/core.h b/qtmips_machine/core.h index b368b3b..386b486 100644 --- a/qtmips_machine/core.h +++ b/qtmips_machine/core.h @@ -21,6 +21,12 @@ public: unsigned cycles(); // Returns number of executed cycles + enum ForwardFrom { + FORWARD_NONE = 0b00, + FORWARD_FROM_W = 0b01, + FORWARD_FROM_M = 0b10, + }; + signals: void instruction_fetched(const machine::Instruction &inst); void instruction_decoded(const machine::Instruction &inst); @@ -43,6 +49,8 @@ signals: void execute_alu_value(std::uint32_t); void execute_reg1_value(std::uint32_t); void execute_reg2_value(std::uint32_t); + void execute_reg1_ff_value(std::uint32_t); + void execute_reg2_ff_value(std::uint32_t); void execute_immediate_value(std::uint32_t); void execute_regw_value(std::uint32_t); void execute_memtoreg_value(std::uint32_t); @@ -81,6 +89,8 @@ protected: enum MemoryAccess::AccessControl memctl; // Decoded memory access type std::uint32_t val_rs; // Value from register rs std::uint32_t val_rt; // Value from register rt + ForwardFrom ff_rs; + ForwardFrom ff_rt; }; struct dtExecute { Instruction inst; |