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authorPavel Pisa <pisa@cmp.felk.cvut.cz>2019-02-06 23:17:47 +0100
committerPavel Pisa <pisa@cmp.felk.cvut.cz>2019-02-06 23:17:47 +0100
commitb232bb867c1ac8cb7369190e8cd4f9f7af425cd1 (patch)
treeb02e07497de7ddf4c70fa335a06c23040559e5d7 /tests/machine-unit-tests
parent9634200c1041eca1c7ac0ce25d79bb8d961530f6 (diff)
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Implemented base for exception handling.
Memory stage is chosen to be exception commit stage. Instructions flow postponed and stages holding following instructions are cleaned. Processing of syscall at decode stage as jump to the handler would be better solution in real hardware but for future emulated syscalls it is better to reach consistent state of registers. Memory access caused exceptions would require cleanup even in real hardware. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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