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authorPavel Pisa <pisa@cmp.felk.cvut.cz>2019-02-11 22:19:23 +0100
committerPavel Pisa <pisa@cmp.felk.cvut.cz>2019-02-11 22:19:23 +0100
commit54d7ef4272673e55b6a4324373d11875280dad84 (patch)
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parentbb7092e96401e4c89c44773c932788c9b0f87b53 (diff)
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Display red background for instruction causing exception and skip HW breakpoint for first cycle after resume.
Instruction for stage is updated when given stage is flushed as well. But other signals are left intact, it is duty of memory stage to discard effect of instruction causing interrupt. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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