diff options
| author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2019-03-05 21:25:24 +0100 |
|---|---|---|
| committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2019-03-05 21:25:24 +0100 |
| commit | 576c4381be6980f95d63ea91f8737dfc22fa8dbe (patch) | |
| tree | 23fc5f9b613babae0c89e4e726649e12317796dd /tests/cpu_trap | |
| parent | 675ede8c34671415bc423e6360ffe0de12d49ec8 (diff) | |
| download | qtmips-576c4381be6980f95d63ea91f8737dfc22fa8dbe.tar.gz qtmips-576c4381be6980f95d63ea91f8737dfc22fa8dbe.tar.bz2 qtmips-576c4381be6980f95d63ea91f8737dfc22fa8dbe.zip | |
Complete revamp of disassembler and assembler arguments processing.
Instructions description in instruction.cpp has been
pragmatically augmented by tool based on Python MIPS simulator,
hazards analyzer
https://github.com/ppisa/apo-simarch
That code has been originally distilled from from GNU
binutils sources.
Implementation is now inline with my original proposal
Previous solution gets untenable with more complex
instructions and its complexity would grow extremely.
MIPS instruction set with coprocessor instructions
which use sel field, rd used as index, rt as destination
and other peculiarities in newer versions cannot
be processed based on basic CPU control signals.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Diffstat (limited to 'tests/cpu_trap')
0 files changed, 0 insertions, 0 deletions