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| author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2019-02-11 22:19:23 +0100 |
|---|---|---|
| committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2019-02-11 22:19:23 +0100 |
| commit | 54d7ef4272673e55b6a4324373d11875280dad84 (patch) | |
| tree | fc59ca3ca89408e6c8ceda594ed9994ffcd5aa90 /tests/cpu_trap/trap.S | |
| parent | bb7092e96401e4c89c44773c932788c9b0f87b53 (diff) | |
| download | qtmips-54d7ef4272673e55b6a4324373d11875280dad84.tar.gz qtmips-54d7ef4272673e55b6a4324373d11875280dad84.tar.bz2 qtmips-54d7ef4272673e55b6a4324373d11875280dad84.zip | |
Display red background for instruction causing exception and skip HW breakpoint for first cycle after resume.
Instruction for stage is updated when given stage is flushed as well.
But other signals are left intact, it is duty of memory stage
to discard effect of instruction causing interrupt.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Diffstat (limited to 'tests/cpu_trap/trap.S')
0 files changed, 0 insertions, 0 deletions