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| author | Karel Kočí <cynerd@email.cz> | 2017-11-21 19:48:51 +0100 |
|---|---|---|
| committer | Karel Kočí <cynerd@email.cz> | 2017-11-21 19:48:51 +0100 |
| commit | 499a88621d12ff0cdcba1f8c796b7031d6adc649 (patch) | |
| tree | c050b5224c896b3e14d74866473aef9c2a5e9b69 /qtmips_machine/tests/testalu.cpp | |
| parent | 68f2af6801756980ec53347c0acb7fcc292f7939 (diff) | |
| download | qtmips-499a88621d12ff0cdcba1f8c796b7031d6adc649.tar.gz qtmips-499a88621d12ff0cdcba1f8c796b7031d6adc649.tar.bz2 qtmips-499a88621d12ff0cdcba1f8c796b7031d6adc649.zip | |
Add possibility to compare memory and registers state
For core testing we want to compare whole memory and registers.
Registers are pretty simple but in case of memory it is some what more
complicated and required its own tests to be sure that it works.
Diffstat (limited to 'qtmips_machine/tests/testalu.cpp')
| -rw-r--r-- | qtmips_machine/tests/testalu.cpp | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/qtmips_machine/tests/testalu.cpp b/qtmips_machine/tests/testalu.cpp index 37accdf..2943906 100644 --- a/qtmips_machine/tests/testalu.cpp +++ b/qtmips_machine/tests/testalu.cpp @@ -3,49 +3,49 @@ #include "qtmipsexception.h" void MachineTests::alu_data() { - QTest::addColumn<std::uint8_t>("op"); + QTest::addColumn<AluOp>("op"); QTest::addColumn<std::uint32_t>("s"); QTest::addColumn<std::uint32_t>("t"); QTest::addColumn<std::uint8_t>("sa"); QTest::addColumn<std::uint32_t>("res"); // TODO SLL-SRAV - QTest::newRow("ADD") << (std::uint8_t)ALU_OP_ADD \ + QTest::newRow("ADD") << ALU_OP_ADD \ << (std::uint32_t)24 \ << (std::uint32_t)66 \ << (std::uint8_t)0 \ << (std::uint32_t)90; - QTest::newRow("ADDU") << (std::uint8_t)ALU_OP_ADDU \ + QTest::newRow("ADDU") << ALU_OP_ADDU \ << (std::uint32_t)24 \ << (std::uint32_t)66 \ << (std::uint8_t)0 \ << (std::uint32_t)90; - QTest::newRow("SUB") << (std::uint8_t)ALU_OP_SUB \ + QTest::newRow("SUB") << ALU_OP_SUB \ << (std::uint32_t)66 \ << (std::uint32_t)24 \ << (std::uint8_t)0 \ << (std::uint32_t)42; - QTest::newRow("SUBU") << (std::uint8_t)ALU_OP_SUBU \ + QTest::newRow("SUBU") << ALU_OP_SUBU \ << (std::uint32_t)24 \ << (std::uint32_t)66 \ << (std::uint8_t)0 \ << (std::uint32_t)-42; - QTest::newRow("AND") << (std::uint8_t)ALU_OP_AND \ + QTest::newRow("AND") << ALU_OP_AND \ << (std::uint32_t)0xA81 \ << (std::uint32_t)0x603 \ << (std::uint8_t)0 \ << (std::uint32_t)0x201; - QTest::newRow("OR") << (std::uint8_t)ALU_OP_OR \ + QTest::newRow("OR") << ALU_OP_OR \ << (std::uint32_t)0xA81 \ << (std::uint32_t)0x603 \ << (std::uint8_t)0 \ << (std::uint32_t)0xE83; - QTest::newRow("XOR") << (std::uint8_t)ALU_OP_XOR \ + QTest::newRow("XOR") << ALU_OP_XOR \ << (std::uint32_t)0xA81 \ << (std::uint32_t)0x603 \ << (std::uint8_t)0 \ << (std::uint32_t)0xC82; - QTest::newRow("NOR") << (std::uint8_t)ALU_OP_NOR \ + QTest::newRow("NOR") << ALU_OP_NOR \ << (std::uint32_t)0xA81 \ << (std::uint32_t)0x603 \ << (std::uint8_t)0 \ @@ -54,13 +54,13 @@ void MachineTests::alu_data() { } void MachineTests::alu() { - QFETCH(std::uint8_t, op); + QFETCH(AluOp, op); QFETCH(std::uint32_t, s); QFETCH(std::uint32_t, t); QFETCH(std::uint8_t, sa); QFETCH(std::uint32_t, res); - QCOMPARE(alu_operate((enum AluOp)op, s , t, sa), res); + QCOMPARE(alu_operate(op, s , t, sa), res); } void MachineTests::alu_except_data() { |