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authorPavel Pisa <pisa@cmp.felk.cvut.cz>2019-02-04 18:13:58 +0100
committerPavel Pisa <pisa@cmp.felk.cvut.cz>2019-02-04 18:13:58 +0100
commit40580e24e7a7b2e774d001878dc493216e75b936 (patch)
treed5fd0e60a09c35111fabe9d8975a8cb2a087b431 /qtmips_machine/memory.cpp
parent36492497ba7096fb20c417941d426e01870d213d (diff)
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Unified instructions table and access type move to machinedefs.h .
This allows to specify requirement for RS and RD on instruction basis even for T_R / ALU instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Diffstat (limited to 'qtmips_machine/memory.cpp')
-rw-r--r--qtmips_machine/memory.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/qtmips_machine/memory.cpp b/qtmips_machine/memory.cpp
index 2df0193..338835d 100644
--- a/qtmips_machine/memory.cpp
+++ b/qtmips_machine/memory.cpp
@@ -75,7 +75,7 @@ std::uint32_t MemoryAccess::read_word(std::uint32_t offset) const {
return rword(offset);
}
-void MemoryAccess::write_ctl(enum MemoryAccess::AccessControl ctl, std::uint32_t offset, std::uint32_t value) {
+void MemoryAccess::write_ctl(enum AccessControl ctl, std::uint32_t offset, std::uint32_t value) {
switch (ctl) {
case AC_NONE:
break;
@@ -95,7 +95,7 @@ void MemoryAccess::write_ctl(enum MemoryAccess::AccessControl ctl, std::uint32_t
}
}
-std::uint32_t MemoryAccess::read_ctl(enum MemoryAccess::AccessControl ctl, std::uint32_t offset) const {
+std::uint32_t MemoryAccess::read_ctl(enum AccessControl ctl, std::uint32_t offset) const {
switch (ctl) {
case AC_NONE:
return 0;