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authorPavel Pisa <pisa@cmp.felk.cvut.cz>2019-03-26 23:40:21 +0100
committerPavel Pisa <pisa@cmp.felk.cvut.cz>2019-03-26 23:40:21 +0100
commitc72e3ad5824eb9385b62a51633cff817b825f06d (patch)
tree7329be83ff8fc8bd0133206ec52e3b4d23e58dad /qtmips_gui/coreview
parent816b01b99eb770958589aadab25cd5e103917003 (diff)
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Change single cycle core with delay slot to use separate fetch stage.
When instructions are visualized then it is even more misleading to keep old instruction in decode phase delay buffer. The single cycle core with delay slot is upgraded to the variant with fetch and execute phases. This way the structure is logical and delay slot has purpose. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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