Change single cycle core with delay slot to use separate fetch stage.

When instructions are visualized then it is even more
misleading to keep old instruction in decode phase delay buffer.

The single cycle core with delay slot is upgraded
to the variant with fetch and execute phases.
This way the structure is logical and delay slot
has purpose.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

0 files changed, 0 insertions, 0 deletions