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authorPavel Pisa <pisa@cmp.felk.cvut.cz>2020-05-11 10:04:17 +0200
committerPavel Pisa <pisa@cmp.felk.cvut.cz>2020-05-11 10:04:17 +0200
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parent4e18ac008b2fa958f16e30b44da097d242d22470 (diff)
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README: correct professor Hennessy name spelling.HEADmaster
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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@@ -20,7 +20,7 @@ The used [MIPS CPU](https://en.wikipedia.org/wiki/MIPS_architecture) building bl
and a pipeline model matches lecture slides prepared by Michal Štepanovský for the subject
[Computer Architectures](https://cw.fel.cvut.cz/wiki/courses/b35apo/start).
The course is based on the book [Computer Organization and Design, The HW/SW Interface](https://www.elsevier.com/books/computer-organization-and-design-mips-edition/patterson/978-0-12-407726-3) written by
-professors Patterson and Henessy.
+professors Patterson and Hennessy.
Additional documentation can be found in subdirectory [`docs`](docs)
of the project.