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| author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2019-02-14 13:24:21 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-02-14 13:24:21 +0100 |
| commit | b4a28dd76b9b3d1eafc87f46635b1a44abd2ac78 (patch) | |
| tree | bfccf9810011db0929c6220aec9cc00209972046 | |
| parent | b8c8760c8618c3d812b3e63a791449b3386cf594 (diff) | |
| download | qtmips-b4a28dd76b9b3d1eafc87f46635b1a44abd2ac78.tar.gz qtmips-b4a28dd76b9b3d1eafc87f46635b1a44abd2ac78.tar.bz2 qtmips-b4a28dd76b9b3d1eafc87f46635b1a44abd2ac78.zip | |
Typo corrected.
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -14,7 +14,7 @@ overview of the project architecture and basic usage information. The used [MIPS CPU](https://en.wikipedia.org/wiki/MIPS_architecture) building block diagram, -and a pipeline model matches lecture slides prepared by Micha Štepanovský for the subject +and a pipeline model matches lecture slides prepared by Michal Štepanovský for the subject [Computer Architectures](https://cw.fel.cvut.cz/wiki/courses/b35apo/start). The course is based on the book [Computer Organization and Design, The HW/SW Interface](https://www.elsevier.com/books/computer-organization-and-design-mips-edition/patterson/978-0-12-407726-3) written by professors Paterson and Henessy. |