blob: 29bb342cec9209be99d428331328b166463075c6 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
|
From 74acdb46ee1c31a4071bc25deaa6a9ed6e10229e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
Date: Fri, 6 May 2022 14:22:28 +0200
Subject: [PATCH 29/53] dt-bindings: irqchip: armada-370-xp: Update information
about MPIC SoC Error
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Signed-off-by: Pali Rohár <pali@kernel.org>
---
.../interrupt-controller/marvell,armada-370-xp-mpic.txt | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt
index 5fc03134a999..8cddbc16ddbd 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt
@@ -24,6 +24,11 @@ Optional properties:
connected as a slave to the Cortex-A9 GIC. The provided interrupt
indicate to which GIC interrupt the MPIC output is connected.
+Optional subnodes:
+
+- interrupt-controller@20 with interrupt-controller property for
+ MPIC SoC Error IRQ controller
+
Example:
mpic: interrupt-controller@d0020000 {
@@ -35,4 +40,8 @@ Example:
msi-controller;
reg = <0xd0020a00 0x1d0>,
<0xd0021070 0x58>;
+ soc_err: interrupt-controller@20 {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
--
2.37.3
|
