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Diffstat (limited to 'pkgs/patches-linux-5.15/784-v5.19-3-net-dsa-mv88e6xxx-convert-to-phylink_generic_validat.patch')
-rw-r--r--pkgs/patches-linux-5.15/784-v5.19-3-net-dsa-mv88e6xxx-convert-to-phylink_generic_validat.patch407
1 files changed, 407 insertions, 0 deletions
diff --git a/pkgs/patches-linux-5.15/784-v5.19-3-net-dsa-mv88e6xxx-convert-to-phylink_generic_validat.patch b/pkgs/patches-linux-5.15/784-v5.19-3-net-dsa-mv88e6xxx-convert-to-phylink_generic_validat.patch
new file mode 100644
index 0000000..ca67edc
--- /dev/null
+++ b/pkgs/patches-linux-5.15/784-v5.19-3-net-dsa-mv88e6xxx-convert-to-phylink_generic_validat.patch
@@ -0,0 +1,407 @@
+From 632d16a663154c8a02810ea266bd6cff31316f9f Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Thu, 3 Feb 2022 13:30:47 +0000
+Subject: [PATCH 3/6] net: dsa: mv88e6xxx: convert to
+ phylink_generic_validate()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Now that the mv88e6xxx chip drivers are supplying the supported
+interfaces and MAC capabilities, switch the driver to use the generic
+phylink validation implementation by removing our own validation
+implementations. This causes DSA to call phylink_generic_validate()
+on our behalf.
+
+Reviewed-by: Marek Behún <kabel@kernel.org>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mv88e6xxx/chip.c | 153 -------------------------------
+ drivers/net/dsa/mv88e6xxx/chip.h | 3 -
+ 2 files changed, 156 deletions(-)
+
+diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
+index c86a08274ca3..7172b3e2e323 100644
+--- a/drivers/net/dsa/mv88e6xxx/chip.c
++++ b/drivers/net/dsa/mv88e6xxx/chip.c
+@@ -563,130 +563,6 @@ static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
+ return 0;
+ }
+
+-static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
+- unsigned long *mask,
+- struct phylink_link_state *state)
+-{
+- if (!phy_interface_mode_is_8023z(state->interface)) {
+- /* 10M and 100M are only supported in non-802.3z mode */
+- phylink_set(mask, 10baseT_Half);
+- phylink_set(mask, 10baseT_Full);
+- phylink_set(mask, 100baseT_Half);
+- phylink_set(mask, 100baseT_Full);
+- }
+-}
+-
+-static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
+- unsigned long *mask,
+- struct phylink_link_state *state)
+-{
+- /* FIXME: if the port is in 1000Base-X mode, then it only supports
+- * 1000M FD speeds. In this case, CMODE will indicate 5.
+- */
+- phylink_set(mask, 1000baseT_Full);
+- phylink_set(mask, 1000baseX_Full);
+-
+- mv88e6065_phylink_validate(chip, port, mask, state);
+-}
+-
+-static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
+- unsigned long *mask,
+- struct phylink_link_state *state)
+-{
+- if (port >= 5)
+- phylink_set(mask, 2500baseX_Full);
+-
+- /* No ethtool bits for 200Mbps */
+- phylink_set(mask, 1000baseT_Full);
+- phylink_set(mask, 1000baseX_Full);
+-
+- mv88e6065_phylink_validate(chip, port, mask, state);
+-}
+-
+-static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
+- unsigned long *mask,
+- struct phylink_link_state *state)
+-{
+- /* No ethtool bits for 200Mbps */
+- phylink_set(mask, 1000baseT_Full);
+- phylink_set(mask, 1000baseX_Full);
+-
+- mv88e6065_phylink_validate(chip, port, mask, state);
+-}
+-
+-static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
+- unsigned long *mask,
+- struct phylink_link_state *state)
+-{
+- if (port >= 9) {
+- phylink_set(mask, 2500baseX_Full);
+- phylink_set(mask, 2500baseT_Full);
+- }
+-
+- /* No ethtool bits for 200Mbps */
+- phylink_set(mask, 1000baseT_Full);
+- phylink_set(mask, 1000baseX_Full);
+-
+- mv88e6065_phylink_validate(chip, port, mask, state);
+-}
+-
+-static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
+- unsigned long *mask,
+- struct phylink_link_state *state)
+-{
+- if (port >= 9) {
+- phylink_set(mask, 10000baseT_Full);
+- phylink_set(mask, 10000baseKR_Full);
+- }
+-
+- mv88e6390_phylink_validate(chip, port, mask, state);
+-}
+-
+-static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
+- unsigned long *mask,
+- struct phylink_link_state *state)
+-{
+- bool is_6191x =
+- chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
+-
+- if (((port == 0 || port == 9) && !is_6191x) || port == 10) {
+- phylink_set(mask, 10000baseT_Full);
+- phylink_set(mask, 10000baseKR_Full);
+- phylink_set(mask, 10000baseCR_Full);
+- phylink_set(mask, 10000baseSR_Full);
+- phylink_set(mask, 10000baseLR_Full);
+- phylink_set(mask, 10000baseLRM_Full);
+- phylink_set(mask, 10000baseER_Full);
+- phylink_set(mask, 5000baseT_Full);
+- phylink_set(mask, 2500baseX_Full);
+- phylink_set(mask, 2500baseT_Full);
+- }
+-
+- phylink_set(mask, 1000baseT_Full);
+- phylink_set(mask, 1000baseX_Full);
+-
+- mv88e6065_phylink_validate(chip, port, mask, state);
+-}
+-
+-static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
+- unsigned long *supported,
+- struct phylink_link_state *state)
+-{
+- __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
+- struct mv88e6xxx_chip *chip = ds->priv;
+-
+- /* Allow all the expected bits */
+- phylink_set(mask, Autoneg);
+- phylink_set(mask, Pause);
+- phylink_set_port_modes(mask);
+-
+- if (chip->info->ops->phylink_validate)
+- chip->info->ops->phylink_validate(chip, port, mask, state);
+-
+- linkmode_and(supported, supported, mask);
+- linkmode_and(state->advertising, state->advertising, mask);
+-}
+-
+ static const u8 mv88e6185_phy_interface_modes[] = {
+ [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII,
+ [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
+@@ -3840,7 +3716,6 @@ static const struct mv88e6xxx_ops mv88e6085_ops = {
+ .vtu_getnext = mv88e6352_g1_vtu_getnext,
+ .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ .phylink_get_caps = mv88e6185_phylink_get_caps,
+- .phylink_validate = mv88e6185_phylink_validate,
+ .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
+ };
+
+@@ -3875,7 +3750,6 @@ static const struct mv88e6xxx_ops mv88e6095_ops = {
+ .vtu_getnext = mv88e6185_g1_vtu_getnext,
+ .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
+ .phylink_get_caps = mv88e6185_phylink_get_caps,
+- .phylink_validate = mv88e6185_phylink_validate,
+ .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
+ };
+
+@@ -3923,7 +3797,6 @@ static const struct mv88e6xxx_ops mv88e6097_ops = {
+ .vtu_getnext = mv88e6352_g1_vtu_getnext,
+ .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ .phylink_get_caps = mv88e6185_phylink_get_caps,
+- .phylink_validate = mv88e6185_phylink_validate,
+ .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
+ };
+
+@@ -3961,7 +3834,6 @@ static const struct mv88e6xxx_ops mv88e6123_ops = {
+ .vtu_getnext = mv88e6352_g1_vtu_getnext,
+ .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ .phylink_get_caps = mv88e6185_phylink_get_caps,
+- .phylink_validate = mv88e6185_phylink_validate,
+ .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
+ };
+
+@@ -4003,7 +3875,6 @@ static const struct mv88e6xxx_ops mv88e6131_ops = {
+ .vtu_getnext = mv88e6185_g1_vtu_getnext,
+ .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
+ .phylink_get_caps = mv88e6185_phylink_get_caps,
+- .phylink_validate = mv88e6185_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6141_ops = {
+@@ -4068,7 +3939,6 @@ static const struct mv88e6xxx_ops mv88e6141_ops = {
+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
+ .serdes_get_regs = mv88e6390_serdes_get_regs,
+ .phylink_get_caps = mv88e6341_phylink_get_caps,
+- .phylink_validate = mv88e6341_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6161_ops = {
+@@ -4111,7 +3981,6 @@ static const struct mv88e6xxx_ops mv88e6161_ops = {
+ .avb_ops = &mv88e6165_avb_ops,
+ .ptp_ops = &mv88e6165_ptp_ops,
+ .phylink_get_caps = mv88e6185_phylink_get_caps,
+- .phylink_validate = mv88e6185_phylink_validate,
+ .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
+ };
+
+@@ -4148,7 +4017,6 @@ static const struct mv88e6xxx_ops mv88e6165_ops = {
+ .avb_ops = &mv88e6165_avb_ops,
+ .ptp_ops = &mv88e6165_ptp_ops,
+ .phylink_get_caps = mv88e6185_phylink_get_caps,
+- .phylink_validate = mv88e6185_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6171_ops = {
+@@ -4191,7 +4059,6 @@ static const struct mv88e6xxx_ops mv88e6171_ops = {
+ .vtu_getnext = mv88e6352_g1_vtu_getnext,
+ .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ .phylink_get_caps = mv88e6185_phylink_get_caps,
+- .phylink_validate = mv88e6185_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6172_ops = {
+@@ -4247,7 +4114,6 @@ static const struct mv88e6xxx_ops mv88e6172_ops = {
+ .serdes_get_regs = mv88e6352_serdes_get_regs,
+ .gpio_ops = &mv88e6352_gpio_ops,
+ .phylink_get_caps = mv88e6352_phylink_get_caps,
+- .phylink_validate = mv88e6352_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6175_ops = {
+@@ -4290,7 +4156,6 @@ static const struct mv88e6xxx_ops mv88e6175_ops = {
+ .vtu_getnext = mv88e6352_g1_vtu_getnext,
+ .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ .phylink_get_caps = mv88e6185_phylink_get_caps,
+- .phylink_validate = mv88e6185_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6176_ops = {
+@@ -4349,7 +4214,6 @@ static const struct mv88e6xxx_ops mv88e6176_ops = {
+ .serdes_get_regs = mv88e6352_serdes_get_regs,
+ .gpio_ops = &mv88e6352_gpio_ops,
+ .phylink_get_caps = mv88e6352_phylink_get_caps,
+- .phylink_validate = mv88e6352_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6185_ops = {
+@@ -4389,7 +4253,6 @@ static const struct mv88e6xxx_ops mv88e6185_ops = {
+ .vtu_getnext = mv88e6185_g1_vtu_getnext,
+ .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
+ .phylink_get_caps = mv88e6185_phylink_get_caps,
+- .phylink_validate = mv88e6185_phylink_validate,
+ .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
+ };
+
+@@ -4452,7 +4315,6 @@ static const struct mv88e6xxx_ops mv88e6190_ops = {
+ .serdes_get_regs = mv88e6390_serdes_get_regs,
+ .gpio_ops = &mv88e6352_gpio_ops,
+ .phylink_get_caps = mv88e6390_phylink_get_caps,
+- .phylink_validate = mv88e6390_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6190x_ops = {
+@@ -4514,7 +4376,6 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = {
+ .serdes_get_regs = mv88e6390_serdes_get_regs,
+ .gpio_ops = &mv88e6352_gpio_ops,
+ .phylink_get_caps = mv88e6390x_phylink_get_caps,
+- .phylink_validate = mv88e6390x_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6191_ops = {
+@@ -4575,7 +4436,6 @@ static const struct mv88e6xxx_ops mv88e6191_ops = {
+ .avb_ops = &mv88e6390_avb_ops,
+ .ptp_ops = &mv88e6352_ptp_ops,
+ .phylink_get_caps = mv88e6390_phylink_get_caps,
+- .phylink_validate = mv88e6390_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6240_ops = {
+@@ -4636,7 +4496,6 @@ static const struct mv88e6xxx_ops mv88e6240_ops = {
+ .avb_ops = &mv88e6352_avb_ops,
+ .ptp_ops = &mv88e6352_ptp_ops,
+ .phylink_get_caps = mv88e6352_phylink_get_caps,
+- .phylink_validate = mv88e6352_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6250_ops = {
+@@ -4677,7 +4536,6 @@ static const struct mv88e6xxx_ops mv88e6250_ops = {
+ .avb_ops = &mv88e6352_avb_ops,
+ .ptp_ops = &mv88e6250_ptp_ops,
+ .phylink_get_caps = mv88e6250_phylink_get_caps,
+- .phylink_validate = mv88e6065_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6290_ops = {
+@@ -4740,7 +4598,6 @@ static const struct mv88e6xxx_ops mv88e6290_ops = {
+ .avb_ops = &mv88e6390_avb_ops,
+ .ptp_ops = &mv88e6352_ptp_ops,
+ .phylink_get_caps = mv88e6390_phylink_get_caps,
+- .phylink_validate = mv88e6390_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6320_ops = {
+@@ -4785,7 +4642,6 @@ static const struct mv88e6xxx_ops mv88e6320_ops = {
+ .avb_ops = &mv88e6352_avb_ops,
+ .ptp_ops = &mv88e6352_ptp_ops,
+ .phylink_get_caps = mv88e6185_phylink_get_caps,
+- .phylink_validate = mv88e6185_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6321_ops = {
+@@ -4828,7 +4684,6 @@ static const struct mv88e6xxx_ops mv88e6321_ops = {
+ .avb_ops = &mv88e6352_avb_ops,
+ .ptp_ops = &mv88e6352_ptp_ops,
+ .phylink_get_caps = mv88e6185_phylink_get_caps,
+- .phylink_validate = mv88e6185_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6341_ops = {
+@@ -4895,7 +4750,6 @@ static const struct mv88e6xxx_ops mv88e6341_ops = {
+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
+ .serdes_get_regs = mv88e6390_serdes_get_regs,
+ .phylink_get_caps = mv88e6341_phylink_get_caps,
+- .phylink_validate = mv88e6341_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6350_ops = {
+@@ -4938,7 +4792,6 @@ static const struct mv88e6xxx_ops mv88e6350_ops = {
+ .vtu_getnext = mv88e6352_g1_vtu_getnext,
+ .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ .phylink_get_caps = mv88e6185_phylink_get_caps,
+- .phylink_validate = mv88e6185_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6351_ops = {
+@@ -4983,7 +4836,6 @@ static const struct mv88e6xxx_ops mv88e6351_ops = {
+ .avb_ops = &mv88e6352_avb_ops,
+ .ptp_ops = &mv88e6352_ptp_ops,
+ .phylink_get_caps = mv88e6185_phylink_get_caps,
+- .phylink_validate = mv88e6185_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6352_ops = {
+@@ -5047,7 +4899,6 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
+ .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
+ .serdes_get_regs = mv88e6352_serdes_get_regs,
+ .phylink_get_caps = mv88e6352_phylink_get_caps,
+- .phylink_validate = mv88e6352_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6390_ops = {
+@@ -5113,7 +4964,6 @@ static const struct mv88e6xxx_ops mv88e6390_ops = {
+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
+ .serdes_get_regs = mv88e6390_serdes_get_regs,
+ .phylink_get_caps = mv88e6390_phylink_get_caps,
+- .phylink_validate = mv88e6390_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6390x_ops = {
+@@ -5178,7 +5028,6 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
+ .avb_ops = &mv88e6390_avb_ops,
+ .ptp_ops = &mv88e6352_ptp_ops,
+ .phylink_get_caps = mv88e6390x_phylink_get_caps,
+- .phylink_validate = mv88e6390x_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6393x_ops = {
+@@ -5243,7 +5092,6 @@ static const struct mv88e6xxx_ops mv88e6393x_ops = {
+ .avb_ops = &mv88e6390_avb_ops,
+ .ptp_ops = &mv88e6352_ptp_ops,
+ .phylink_get_caps = mv88e6393x_phylink_get_caps,
+- .phylink_validate = mv88e6393x_phylink_validate,
+ };
+
+ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
+@@ -6513,7 +6361,6 @@ static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
+ .port_setup = mv88e6xxx_port_setup,
+ .port_teardown = mv88e6xxx_port_teardown,
+ .phylink_get_caps = mv88e6xxx_get_caps,
+- .phylink_validate = mv88e6xxx_validate,
+ .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
+ .phylink_mac_config = mv88e6xxx_mac_config,
+ .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
+diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h
+index 5b0ee59b3c94..3a685d0cf07c 100644
+--- a/drivers/net/dsa/mv88e6xxx/chip.h
++++ b/drivers/net/dsa/mv88e6xxx/chip.h
+@@ -611,9 +611,6 @@ struct mv88e6xxx_ops {
+ /* Phylink */
+ void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port,
+ struct phylink_config *config);
+- void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
+- unsigned long *mask,
+- struct phylink_link_state *state);
+
+ /* Max Frame Size */
+ int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu);
+--
+2.35.1
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-19 01:11:09 +0000