diff options
Diffstat (limited to 'pkgs/patches-linux-5.15/0024-PCI-pci-bridge-emul-Re-arrange-register-tests.patch')
| -rw-r--r-- | pkgs/patches-linux-5.15/0024-PCI-pci-bridge-emul-Re-arrange-register-tests.patch | 117 |
1 files changed, 117 insertions, 0 deletions
diff --git a/pkgs/patches-linux-5.15/0024-PCI-pci-bridge-emul-Re-arrange-register-tests.patch b/pkgs/patches-linux-5.15/0024-PCI-pci-bridge-emul-Re-arrange-register-tests.patch new file mode 100644 index 0000000..6fee553 --- /dev/null +++ b/pkgs/patches-linux-5.15/0024-PCI-pci-bridge-emul-Re-arrange-register-tests.patch @@ -0,0 +1,117 @@ +From fd539c7270dca28ee9943f7b93d445481ab71721 Mon Sep 17 00:00:00 2001 +From: Russell King <rmk+kernel@armlinux.org.uk> +Date: Tue, 2 Feb 2021 13:45:28 +0000 +Subject: [PATCH 24/90] PCI: pci-bridge-emul: Re-arrange register tests +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Re-arrange the tests for which sets of registers are being accessed so that +it is easier to add further regions later. No functional change. + +Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> +[pali: Fix reading old value in pci_bridge_emul_conf_write] +Signed-off-by: Pali Rohár <pali@kernel.org> +Signed-off-by: Marek Behún <kabel@kernel.org> +--- + drivers/pci/pci-bridge-emul.c | 61 ++++++++++++++++++----------------- + 1 file changed, 31 insertions(+), 30 deletions(-) + +diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c +index a16f9e30099e..a956408834d6 100644 +--- a/drivers/pci/pci-bridge-emul.c ++++ b/drivers/pci/pci-bridge-emul.c +@@ -422,25 +422,25 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where, + __le32 *cfgspace; + const struct pci_bridge_reg_behavior *behavior; + +- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) { +- *value = 0; +- return PCIBIOS_SUCCESSFUL; +- } +- +- if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) { ++ if (reg < PCI_BRIDGE_CONF_END) { ++ /* Emulated PCI space */ ++ read_op = bridge->ops->read_base; ++ cfgspace = (__le32 *) &bridge->conf; ++ behavior = bridge->pci_regs_behavior; ++ } else if (!bridge->has_pcie) { ++ /* PCIe space is not implemented, and no PCI capabilities */ + *value = 0; + return PCIBIOS_SUCCESSFUL; +- } +- +- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { ++ } else if (reg < PCI_CAP_PCIE_END) { ++ /* Our emulated PCIe capability */ + reg -= PCI_CAP_PCIE_START; + read_op = bridge->ops->read_pcie; + cfgspace = (__le32 *) &bridge->pcie_conf; + behavior = bridge->pcie_cap_regs_behavior; + } else { +- read_op = bridge->ops->read_base; +- cfgspace = (__le32 *) &bridge->conf; +- behavior = bridge->pci_regs_behavior; ++ /* Beyond our PCIe space */ ++ *value = 0; ++ return PCIBIOS_SUCCESSFUL; + } + + if (read_op) +@@ -484,11 +484,27 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, + __le32 *cfgspace; + const struct pci_bridge_reg_behavior *behavior; + +- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) +- return PCIBIOS_SUCCESSFUL; ++ ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old); ++ if (ret != PCIBIOS_SUCCESSFUL) ++ return ret; + +- if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) ++ if (reg < PCI_BRIDGE_CONF_END) { ++ /* Emulated PCI space */ ++ write_op = bridge->ops->write_base; ++ cfgspace = (__le32 *) &bridge->conf; ++ behavior = bridge->pci_regs_behavior; ++ } else if (!bridge->has_pcie) { ++ /* PCIe space is not implemented, and no PCI capabilities */ + return PCIBIOS_SUCCESSFUL; ++ } else if (reg < PCI_CAP_PCIE_END) { ++ /* Our emulated PCIe capability */ ++ reg -= PCI_CAP_PCIE_START; ++ write_op = bridge->ops->write_pcie; ++ cfgspace = (__le32 *) &bridge->pcie_conf; ++ behavior = bridge->pcie_cap_regs_behavior; ++ } else { ++ return PCIBIOS_SUCCESSFUL; ++ } + + shift = (where & 0x3) * 8; + +@@ -501,21 +517,6 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, + else + return PCIBIOS_BAD_REGISTER_NUMBER; + +- ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old); +- if (ret != PCIBIOS_SUCCESSFUL) +- return ret; +- +- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { +- reg -= PCI_CAP_PCIE_START; +- write_op = bridge->ops->write_pcie; +- cfgspace = (__le32 *) &bridge->pcie_conf; +- behavior = bridge->pcie_cap_regs_behavior; +- } else { +- write_op = bridge->ops->write_base; +- cfgspace = (__le32 *) &bridge->conf; +- behavior = bridge->pci_regs_behavior; +- } +- + /* Keep all bits, except the RW bits */ + new = old & (~mask | ~behavior[reg / 4].rw); + +-- +2.34.1 + |