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| author | Karel Kočí <cynerd@email.cz> | 2022-10-15 23:01:29 +0200 |
|---|---|---|
| committer | Karel Kočí <cynerd@email.cz> | 2022-10-16 13:20:32 +0200 |
| commit | 462a088c474832b19ff2730de1e6bea66d399c23 (patch) | |
| tree | a512b3b451afde09a9cb06449bd7a3bdc5a8bdb4 /pkgs/patches-linux-5.15/777-v5.16-3-net-ethernet-use-phylink_set_10g_modes.patch | |
| parent | d5514ca4aeddc711639f46024528becfff7c2a70 (diff) | |
| download | nixturris-462a088c474832b19ff2730de1e6bea66d399c23.tar.gz nixturris-462a088c474832b19ff2730de1e6bea66d399c23.tar.bz2 nixturris-462a088c474832b19ff2730de1e6bea66d399c23.zip | |
Add Turris kernel (includes patches from OpenWrt)
Diffstat (limited to 'pkgs/patches-linux-5.15/777-v5.16-3-net-ethernet-use-phylink_set_10g_modes.patch')
| -rw-r--r-- | pkgs/patches-linux-5.15/777-v5.16-3-net-ethernet-use-phylink_set_10g_modes.patch | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/pkgs/patches-linux-5.15/777-v5.16-3-net-ethernet-use-phylink_set_10g_modes.patch b/pkgs/patches-linux-5.15/777-v5.16-3-net-ethernet-use-phylink_set_10g_modes.patch new file mode 100644 index 0000000..0095d64 --- /dev/null +++ b/pkgs/patches-linux-5.15/777-v5.16-3-net-ethernet-use-phylink_set_10g_modes.patch @@ -0,0 +1,74 @@ +From 8259f96b710a2dd78e85bb46f12372dc0a3e75a0 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk> +Date: Mon, 4 Oct 2021 12:03:33 +0100 +Subject: [PATCH 3/3] net: ethernet: use phylink_set_10g_modes() + +Update three drivers to use the new phylink_set_10g_modes() helper: +Cadence macb, Freescale DPAA2 and Marvell PP2. + +Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> +Signed-off-by: David S. Miller <davem@davemloft.net> +--- + drivers/net/ethernet/cadence/macb_main.c | 7 +------ + drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c | 7 +------ + drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 7 +------ + 3 files changed, 3 insertions(+), 18 deletions(-) + +diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c +index c6f28b084646..97941cdfe1a1 100644 +--- a/drivers/net/ethernet/cadence/macb_main.c ++++ b/drivers/net/ethernet/cadence/macb_main.c +@@ -548,13 +548,8 @@ static void macb_validate(struct phylink_config *config, + if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE && + (state->interface == PHY_INTERFACE_MODE_NA || + state->interface == PHY_INTERFACE_MODE_10GBASER)) { +- phylink_set(mask, 10000baseCR_Full); +- phylink_set(mask, 10000baseER_Full); ++ phylink_set_10g_modes(mask); + phylink_set(mask, 10000baseKR_Full); +- phylink_set(mask, 10000baseLR_Full); +- phylink_set(mask, 10000baseLRM_Full); +- phylink_set(mask, 10000baseSR_Full); +- phylink_set(mask, 10000baseT_Full); + if (state->interface != PHY_INTERFACE_MODE_NA) + goto out; + } +diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c +index 543c1f202420..ef8f0a055024 100644 +--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c ++++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c +@@ -139,12 +139,7 @@ static void dpaa2_mac_validate(struct phylink_config *config, + case PHY_INTERFACE_MODE_NA: + case PHY_INTERFACE_MODE_10GBASER: + case PHY_INTERFACE_MODE_USXGMII: +- phylink_set(mask, 10000baseT_Full); +- phylink_set(mask, 10000baseCR_Full); +- phylink_set(mask, 10000baseSR_Full); +- phylink_set(mask, 10000baseLR_Full); +- phylink_set(mask, 10000baseLRM_Full); +- phylink_set(mask, 10000baseER_Full); ++ phylink_set_10g_modes(mask); + if (state->interface == PHY_INTERFACE_MODE_10GBASER) + break; + phylink_set(mask, 5000baseT_Full); +diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +index c963115558cb..3c267a94f1ca 100644 +--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c ++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +@@ -6305,12 +6305,7 @@ static void mvpp2_phylink_validate(struct phylink_config *config, + case PHY_INTERFACE_MODE_XAUI: + case PHY_INTERFACE_MODE_NA: + if (mvpp2_port_supports_xlg(port)) { +- phylink_set(mask, 10000baseT_Full); +- phylink_set(mask, 10000baseCR_Full); +- phylink_set(mask, 10000baseSR_Full); +- phylink_set(mask, 10000baseLR_Full); +- phylink_set(mask, 10000baseLRM_Full); +- phylink_set(mask, 10000baseER_Full); ++ phylink_set_10g_modes(mask); + phylink_set(mask, 10000baseKR_Full); + } + if (state->interface != PHY_INTERFACE_MODE_NA) +-- +2.35.1 + |