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authorKarel Kočí <cynerd@email.cz>2022-10-15 23:01:29 +0200
committerKarel Kočí <cynerd@email.cz>2022-10-16 13:20:32 +0200
commit462a088c474832b19ff2730de1e6bea66d399c23 (patch)
treea512b3b451afde09a9cb06449bd7a3bdc5a8bdb4 /pkgs/patches-linux-5.15/0071-dt-bindings-irqchip-armada-370-xp-Update-information.patch
parentd5514ca4aeddc711639f46024528becfff7c2a70 (diff)
downloadnixturris-462a088c474832b19ff2730de1e6bea66d399c23.tar.gz
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Add Turris kernel (includes patches from OpenWrt)
Diffstat (limited to 'pkgs/patches-linux-5.15/0071-dt-bindings-irqchip-armada-370-xp-Update-information.patch')
-rw-r--r--pkgs/patches-linux-5.15/0071-dt-bindings-irqchip-armada-370-xp-Update-information.patch42
1 files changed, 42 insertions, 0 deletions
diff --git a/pkgs/patches-linux-5.15/0071-dt-bindings-irqchip-armada-370-xp-Update-information.patch b/pkgs/patches-linux-5.15/0071-dt-bindings-irqchip-armada-370-xp-Update-information.patch
new file mode 100644
index 0000000..2819708
--- /dev/null
+++ b/pkgs/patches-linux-5.15/0071-dt-bindings-irqchip-armada-370-xp-Update-information.patch
@@ -0,0 +1,42 @@
+From 7324692109764dbd416a308e796ef1d463d07100 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
+Date: Fri, 6 May 2022 14:22:28 +0200
+Subject: [PATCH 71/90] dt-bindings: irqchip: armada-370-xp: Update information
+ about MPIC SoC Error
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Pali Rohár <pali@kernel.org>
+---
+ .../interrupt-controller/marvell,armada-370-xp-mpic.txt | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt
+index 5fc03134a999..8cddbc16ddbd 100644
+--- a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt
++++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt
+@@ -24,6 +24,11 @@ Optional properties:
+ connected as a slave to the Cortex-A9 GIC. The provided interrupt
+ indicate to which GIC interrupt the MPIC output is connected.
+
++Optional subnodes:
++
++- interrupt-controller@20 with interrupt-controller property for
++ MPIC SoC Error IRQ controller
++
+ Example:
+
+ mpic: interrupt-controller@d0020000 {
+@@ -35,4 +40,8 @@ Example:
+ msi-controller;
+ reg = <0xd0020a00 0x1d0>,
+ <0xd0021070 0x58>;
++ soc_err: interrupt-controller@20 {
++ interrupt-controller;
++ #interrupt-cells = <1>;
++ };
+ };
+--
+2.34.1
+