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| author | Karel Kočí <cynerd@email.cz> | 2022-10-15 23:01:29 +0200 |
|---|---|---|
| committer | Karel Kočí <cynerd@email.cz> | 2022-10-16 13:20:32 +0200 |
| commit | 462a088c474832b19ff2730de1e6bea66d399c23 (patch) | |
| tree | a512b3b451afde09a9cb06449bd7a3bdc5a8bdb4 /pkgs/patches-linux-5.15/0043-ARM-dts-armada-380.dtsi-Add-definitions-for-PCIe-leg.patch | |
| parent | d5514ca4aeddc711639f46024528becfff7c2a70 (diff) | |
| download | nixturris-462a088c474832b19ff2730de1e6bea66d399c23.tar.gz nixturris-462a088c474832b19ff2730de1e6bea66d399c23.tar.bz2 nixturris-462a088c474832b19ff2730de1e6bea66d399c23.zip | |
Add Turris kernel (includes patches from OpenWrt)
Diffstat (limited to 'pkgs/patches-linux-5.15/0043-ARM-dts-armada-380.dtsi-Add-definitions-for-PCIe-leg.patch')
| -rw-r--r-- | pkgs/patches-linux-5.15/0043-ARM-dts-armada-380.dtsi-Add-definitions-for-PCIe-leg.patch | 108 |
1 files changed, 108 insertions, 0 deletions
diff --git a/pkgs/patches-linux-5.15/0043-ARM-dts-armada-380.dtsi-Add-definitions-for-PCIe-leg.patch b/pkgs/patches-linux-5.15/0043-ARM-dts-armada-380.dtsi-Add-definitions-for-PCIe-leg.patch new file mode 100644 index 0000000..319396c --- /dev/null +++ b/pkgs/patches-linux-5.15/0043-ARM-dts-armada-380.dtsi-Add-definitions-for-PCIe-leg.patch @@ -0,0 +1,108 @@ +From c13a941742f4496f0a73ccc9f1fcb535548d7067 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> +Date: Mon, 27 Jun 2022 17:39:06 +0200 +Subject: [PATCH 43/90] ARM: dts: armada-380.dtsi: Add definitions for PCIe + legacy INTx interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár <pali@kernel.org> +--- + arch/arm/boot/dts/armada-380.dtsi | 42 ++++++++++++++++++++++++++----- + 1 file changed, 36 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi +index cff1269f3fbf..ce1dddb2269b 100644 +--- a/arch/arm/boot/dts/armada-380.dtsi ++++ b/arch/arm/boot/dts/armada-380.dtsi +@@ -64,16 +64,26 @@ pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie1_intc 0>, ++ <0 0 0 2 &pcie1_intc 1>, ++ <0 0 0 3 &pcie1_intc 2>, ++ <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 8>; + status = "disabled"; ++ ++ pcie1_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + /* x1 port */ +@@ -83,16 +93,26 @@ pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie2_intc 0>, ++ <0 0 0 2 &pcie2_intc 1>, ++ <0 0 0 3 &pcie2_intc 2>, ++ <0 0 0 4 &pcie2_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; ++ ++ pcie2_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + + /* x1 port */ +@@ -102,16 +122,26 @@ pcie@3,0 { + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; ++ interrupt-names = "intx"; ++ interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie3_intc 0>, ++ <0 0 0 2 &pcie3_intc 1>, ++ <0 0 0 3 &pcie3_intc 2>, ++ <0 0 0 4 &pcie3_intc 3>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 6>; + status = "disabled"; ++ ++ pcie3_intc: interrupt-controller { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; + }; + }; +-- +2.34.1 + |