Add Turris kernel (includes patches from OpenWrt)

1 files changed, 79 insertions, 0 deletions

diff --git a/pkgs/patches-linux-5.15/0033-PCI-mvebu-Fix-macro-names-and-comments-about-legacy-.patch b/pkgs/patches-linux-5.15/0033-PCI-mvebu-Fix-macro-names-and-comments-about-legacy-.patch
new file mode 100644
index 0000000..185b1c2
--- /dev/null
+++ b/pkgs/patches-linux-5.15/0033-PCI-mvebu-Fix-macro-names-and-comments-about-legacy-.patch
@@ -0,0 +1,79 @@
+From 8fa82d166233f0c6b4ec82b4b92dbb356cd69675 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
+Date: Mon, 14 Feb 2022 13:12:48 +0100
+Subject: [PATCH 33/90] PCI: mvebu: Fix macro names and comments about legacy
+ interrupts
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Register 0x1910 unmasks interrupts and legacy INTx interrupts are unmasked
+because driver does not support individual masking yet.
+
+Signed-off-by: Pali Rohár <pali@kernel.org>
+---
+ drivers/pci/controller/pci-mvebu.c | 26 ++++++++++++++++++--------
+ 1 file changed, 18 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
+index 1e90ab888075..5f8b8b4ddbea 100644
+--- a/drivers/pci/controller/pci-mvebu.c
++++ b/drivers/pci/controller/pci-mvebu.c
+@@ -54,9 +54,10 @@
+ 	 PCIE_CONF_ADDR_EN)
+ #define PCIE_CONF_DATA_OFF	0x18fc
+ #define PCIE_INT_CAUSE_OFF	0x1900
++#define PCIE_INT_UNMASK_OFF	0x1910
++#define  PCIE_INT_INTX(i)		BIT(24+i)
+ #define  PCIE_INT_PM_PME		BIT(28)
+-#define PCIE_MASK_OFF		0x1910
+-#define  PCIE_MASK_ENABLE_INTS          0x0f000000
++#define  PCIE_INT_ALL_MASK		GENMASK(31, 0)
+ #define PCIE_CTRL_OFF		0x1a00
+ #define  PCIE_CTRL_X1_MODE		0x0001
+ #define  PCIE_CTRL_RC_MODE		BIT(1)
+@@ -235,7 +236,7 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
+ 
+ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
+ {
+-	u32 ctrl, lnkcap, cmd, dev_rev, mask;
++	u32 ctrl, lnkcap, cmd, dev_rev, unmask;
+ 
+ 	/* Setup PCIe controller to Root Complex mode. */
+ 	ctrl = mvebu_readl(port, PCIE_CTRL_OFF);
+@@ -288,10 +289,19 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
+ 	/* Point PCIe unit MBUS decode windows to DRAM space. */
+ 	mvebu_pcie_setup_wins(port);
+ 
+-	/* Enable interrupt lines A-D. */
+-	mask = mvebu_readl(port, PCIE_MASK_OFF);
+-	mask |= PCIE_MASK_ENABLE_INTS;
+-	mvebu_writel(port, mask, PCIE_MASK_OFF);
++	/*
++	 * Unmask all legacy INTx interrupts as driver does not provide a way
++	 * for masking and unmasking of individual legacy INTx interrupts.
++	 * Legacy INTx are reported via one shared GIC source and therefore
++	 * kernel cannot distinguish which individual legacy INTx was triggered.
++	 * These interrupts are shared, so it should not cause any issue. Just
++	 * performance penalty as every PCIe interrupt handler needs to be
++	 * called when some interrupt is triggered.
++	 */
++	unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF);
++	unmask |= PCIE_INT_INTX(0) | PCIE_INT_INTX(1) |
++		  PCIE_INT_INTX(2) | PCIE_INT_INTX(3);
++	mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF);
+ }
+ 
+ static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
+@@ -1458,7 +1468,7 @@ static int mvebu_pcie_remove(struct platform_device *pdev)
+ 		mvebu_writel(port, cmd, PCIE_CMD_OFF);
+ 
+ 		/* Mask all interrupt sources. */
+-		mvebu_writel(port, 0, PCIE_MASK_OFF);
++		mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF);
+ 
+ 		/* Free config space for emulated root bridge. */
+ 		pci_bridge_emul_cleanup(&port->bridge);
+-- 
+2.34.1
+