nixos: try to fix Turris Omnia PCIe on Linux 6.0

Unfortunatelly this seems to not work.

1 files changed, 282 insertions, 0 deletions

diff --git a/nixos/modules/omnia-kernel-patches/0006-ARM-dts-armada-xp-mv78260.dtsi-Add-definitions-for-P.patch b/nixos/modules/omnia-kernel-patches/0006-ARM-dts-armada-xp-mv78260.dtsi-Add-definitions-for-P.patch
new file mode 100644
index 0000000..4830205
--- /dev/null
+++ b/nixos/modules/omnia-kernel-patches/0006-ARM-dts-armada-xp-mv78260.dtsi-Add-definitions-for-P.patch
@@ -0,0 +1,282 @@
+From 7231e882cb8da99ebc2e04e28ade32cffecd33d4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
+Date: Mon, 27 Jun 2022 19:54:06 +0200
+Subject: [PATCH 06/53] ARM: dts: armada-xp-mv78260.dtsi: Add definitions for
+ PCIe legacy INTx interrupts
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Pali Rohár <pali@kernel.org>
+---
+ arch/arm/boot/dts/armada-xp-mv78260.dtsi | 126 +++++++++++++++++++----
+ 1 file changed, 108 insertions(+), 18 deletions(-)
+
+diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+index 2d85fe8ac327..0714af52e607 100644
+--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
++++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+@@ -98,16 +98,26 @@ pcie1: pcie@1,0 {
+ 				reg = <0x0800 0 0 0 0>;
+ 				#address-cells = <3>;
+ 				#size-cells = <2>;
++				interrupt-names = "intx";
++				interrupts-extended = <&mpic 58>;
+ 				#interrupt-cells = <1>;
+ 				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+ 					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ 				bus-range = <0x00 0xff>;
+-				interrupt-map-mask = <0 0 0 0>;
+-				interrupt-map = <0 0 0 0 &mpic 58>;
++				interrupt-map-mask = <0 0 0 7>;
++				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
++						<0 0 0 2 &pcie1_intc 1>,
++						<0 0 0 3 &pcie1_intc 2>,
++						<0 0 0 4 &pcie1_intc 3>;
+ 				marvell,pcie-port = <0>;
+ 				marvell,pcie-lane = <0>;
+ 				clocks = <&gateclk 5>;
+ 				status = "disabled";
++
++				pcie1_intc: interrupt-controller {
++					interrupt-controller;
++					#interrupt-cells = <1>;
++				};
+ 			};
+ 
+ 			pcie2: pcie@2,0 {
+@@ -116,16 +126,26 @@ pcie2: pcie@2,0 {
+ 				reg = <0x1000 0 0 0 0>;
+ 				#address-cells = <3>;
+ 				#size-cells = <2>;
++				interrupt-names = "intx";
++				interrupts-extended = <&mpic 59>;
+ 				#interrupt-cells = <1>;
+ 				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+ 					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
+ 				bus-range = <0x00 0xff>;
+-				interrupt-map-mask = <0 0 0 0>;
+-				interrupt-map = <0 0 0 0 &mpic 59>;
++				interrupt-map-mask = <0 0 0 7>;
++				interrupt-map = <0 0 0 1 &pcie2_intc 0>,
++						<0 0 0 2 &pcie2_intc 1>,
++						<0 0 0 3 &pcie2_intc 2>,
++						<0 0 0 4 &pcie2_intc 3>;
+ 				marvell,pcie-port = <0>;
+ 				marvell,pcie-lane = <1>;
+ 				clocks = <&gateclk 6>;
+ 				status = "disabled";
++
++				pcie2_intc: interrupt-controller {
++					interrupt-controller;
++					#interrupt-cells = <1>;
++				};
+ 			};
+ 
+ 			pcie3: pcie@3,0 {
+@@ -134,16 +154,26 @@ pcie3: pcie@3,0 {
+ 				reg = <0x1800 0 0 0 0>;
+ 				#address-cells = <3>;
+ 				#size-cells = <2>;
++				interrupt-names = "intx";
++				interrupts-extended = <&mpic 60>;
+ 				#interrupt-cells = <1>;
+ 				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+ 					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
+ 				bus-range = <0x00 0xff>;
+-				interrupt-map-mask = <0 0 0 0>;
+-				interrupt-map = <0 0 0 0 &mpic 60>;
++				interrupt-map-mask = <0 0 0 7>;
++				interrupt-map = <0 0 0 1 &pcie3_intc 0>,
++						<0 0 0 2 &pcie3_intc 1>,
++						<0 0 0 3 &pcie3_intc 2>,
++						<0 0 0 4 &pcie3_intc 3>;
+ 				marvell,pcie-port = <0>;
+ 				marvell,pcie-lane = <2>;
+ 				clocks = <&gateclk 7>;
+ 				status = "disabled";
++
++				pcie3_intc: interrupt-controller {
++					interrupt-controller;
++					#interrupt-cells = <1>;
++				};
+ 			};
+ 
+ 			pcie4: pcie@4,0 {
+@@ -152,16 +182,26 @@ pcie4: pcie@4,0 {
+ 				reg = <0x2000 0 0 0 0>;
+ 				#address-cells = <3>;
+ 				#size-cells = <2>;
++				interrupt-names = "intx";
++				interrupts-extended = <&mpic 61>;
+ 				#interrupt-cells = <1>;
+ 				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+ 					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
+ 				bus-range = <0x00 0xff>;
+-				interrupt-map-mask = <0 0 0 0>;
+-				interrupt-map = <0 0 0 0 &mpic 61>;
++				interrupt-map-mask = <0 0 0 7>;
++				interrupt-map = <0 0 0 1 &pcie4_intc 0>,
++						<0 0 0 2 &pcie4_intc 1>,
++						<0 0 0 3 &pcie4_intc 2>,
++						<0 0 0 4 &pcie4_intc 3>;
+ 				marvell,pcie-port = <0>;
+ 				marvell,pcie-lane = <3>;
+ 				clocks = <&gateclk 8>;
+ 				status = "disabled";
++
++				pcie4_intc: interrupt-controller {
++					interrupt-controller;
++					#interrupt-cells = <1>;
++				};
+ 			};
+ 
+ 			pcie5: pcie@5,0 {
+@@ -170,16 +210,26 @@ pcie5: pcie@5,0 {
+ 				reg = <0x2800 0 0 0 0>;
+ 				#address-cells = <3>;
+ 				#size-cells = <2>;
++				interrupt-names = "intx";
++				interrupts-extended = <&mpic 62>;
+ 				#interrupt-cells = <1>;
+ 				ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
+ 					  0x81000000 0 0 0x81000000 0x5 0 1 0>;
+ 				bus-range = <0x00 0xff>;
+-				interrupt-map-mask = <0 0 0 0>;
+-				interrupt-map = <0 0 0 0 &mpic 62>;
++				interrupt-map-mask = <0 0 0 7>;
++				interrupt-map = <0 0 0 1 &pcie5_intc 0>,
++						<0 0 0 2 &pcie5_intc 1>,
++						<0 0 0 3 &pcie5_intc 2>,
++						<0 0 0 4 &pcie5_intc 3>;
+ 				marvell,pcie-port = <1>;
+ 				marvell,pcie-lane = <0>;
+ 				clocks = <&gateclk 9>;
+ 				status = "disabled";
++
++				pcie5_intc: interrupt-controller {
++					interrupt-controller;
++					#interrupt-cells = <1>;
++				};
+ 			};
+ 
+ 			pcie6: pcie@6,0 {
+@@ -188,16 +238,26 @@ pcie6: pcie@6,0 {
+ 				reg = <0x3000 0 0 0 0>;
+ 				#address-cells = <3>;
+ 				#size-cells = <2>;
++				interrupt-names = "intx";
++				interrupts-extended = <&mpic 63>;
+ 				#interrupt-cells = <1>;
+ 				ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
+ 					  0x81000000 0 0 0x81000000 0x6 0 1 0>;
+ 				bus-range = <0x00 0xff>;
+-				interrupt-map-mask = <0 0 0 0>;
+-				interrupt-map = <0 0 0 0 &mpic 63>;
++				interrupt-map-mask = <0 0 0 7>;
++				interrupt-map = <0 0 0 1 &pcie6_intc 0>,
++						<0 0 0 2 &pcie6_intc 1>,
++						<0 0 0 3 &pcie6_intc 2>,
++						<0 0 0 4 &pcie6_intc 3>;
+ 				marvell,pcie-port = <1>;
+ 				marvell,pcie-lane = <1>;
+ 				clocks = <&gateclk 10>;
+ 				status = "disabled";
++
++				pcie6_intc: interrupt-controller {
++					interrupt-controller;
++					#interrupt-cells = <1>;
++				};
+ 			};
+ 
+ 			pcie7: pcie@7,0 {
+@@ -206,16 +266,26 @@ pcie7: pcie@7,0 {
+ 				reg = <0x3800 0 0 0 0>;
+ 				#address-cells = <3>;
+ 				#size-cells = <2>;
++				interrupt-names = "intx";
++				interrupts-extended = <&mpic 64>;
+ 				#interrupt-cells = <1>;
+ 				ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
+ 					  0x81000000 0 0 0x81000000 0x7 0 1 0>;
+ 				bus-range = <0x00 0xff>;
+-				interrupt-map-mask = <0 0 0 0>;
+-				interrupt-map = <0 0 0 0 &mpic 64>;
++				interrupt-map-mask = <0 0 0 7>;
++				interrupt-map = <0 0 0 1 &pcie7_intc 0>,
++						<0 0 0 2 &pcie7_intc 1>,
++						<0 0 0 3 &pcie7_intc 2>,
++						<0 0 0 4 &pcie7_intc 3>;
+ 				marvell,pcie-port = <1>;
+ 				marvell,pcie-lane = <2>;
+ 				clocks = <&gateclk 11>;
+ 				status = "disabled";
++
++				pcie7_intc: interrupt-controller {
++					interrupt-controller;
++					#interrupt-cells = <1>;
++				};
+ 			};
+ 
+ 			pcie8: pcie@8,0 {
+@@ -224,16 +294,26 @@ pcie8: pcie@8,0 {
+ 				reg = <0x4000 0 0 0 0>;
+ 				#address-cells = <3>;
+ 				#size-cells = <2>;
++				interrupt-names = "intx";
++				interrupts-extended = <&mpic 65>;
+ 				#interrupt-cells = <1>;
+ 				ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
+ 					  0x81000000 0 0 0x81000000 0x8 0 1 0>;
+ 				bus-range = <0x00 0xff>;
+-				interrupt-map-mask = <0 0 0 0>;
+-				interrupt-map = <0 0 0 0 &mpic 65>;
++				interrupt-map-mask = <0 0 0 7>;
++				interrupt-map = <0 0 0 1 &pcie8_intc 0>,
++						<0 0 0 2 &pcie8_intc 1>,
++						<0 0 0 3 &pcie8_intc 2>,
++						<0 0 0 4 &pcie8_intc 3>;
+ 				marvell,pcie-port = <1>;
+ 				marvell,pcie-lane = <3>;
+ 				clocks = <&gateclk 12>;
+ 				status = "disabled";
++
++				pcie8_intc: interrupt-controller {
++					interrupt-controller;
++					#interrupt-cells = <1>;
++				};
+ 			};
+ 
+ 			pcie9: pcie@9,0 {
+@@ -242,16 +322,26 @@ pcie9: pcie@9,0 {
+ 				reg = <0x4800 0 0 0 0>;
+ 				#address-cells = <3>;
+ 				#size-cells = <2>;
++				interrupt-names = "intx";
++				interrupts-extended = <&mpic 99>;
+ 				#interrupt-cells = <1>;
+ 				ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
+ 					  0x81000000 0 0 0x81000000 0x9 0 1 0>;
+ 				bus-range = <0x00 0xff>;
+-				interrupt-map-mask = <0 0 0 0>;
+-				interrupt-map = <0 0 0 0 &mpic 99>;
++				interrupt-map-mask = <0 0 0 7>;
++				interrupt-map = <0 0 0 1 &pcie9_intc 0>,
++						<0 0 0 2 &pcie9_intc 1>,
++						<0 0 0 3 &pcie9_intc 2>,
++						<0 0 0 4 &pcie9_intc 3>;
+ 				marvell,pcie-port = <2>;
+ 				marvell,pcie-lane = <0>;
+ 				clocks = <&gateclk 26>;
+ 				status = "disabled";
++
++				pcie9_intc: interrupt-controller {
++					interrupt-controller;
++					#interrupt-cells = <1>;
++				};
+ 			};
+ 		};
+ 
+-- 
+2.37.3
+