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author | Karel Kočí <cynerd@email.cz> | 2016-06-30 16:03:25 +0200 |
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committer | Karel Kočí <cynerd@email.cz> | 2016-06-30 16:03:25 +0200 |
commit | e573b3020c032400eed60b649a2cbf55266e6bb0 (patch) | |
tree | 8f572394ac8433529c7a8e70d160a2fbe8268b4e /vim/bundle/vim-snippets/snippets/systemverilog.snippets | |
parent | b8c667bd64b3edd38d56c63c5bd1db53a23b4499 (diff) | |
download | myconfigs-e573b3020c032400eed60b649a2cbf55266e6bb0.tar.gz myconfigs-e573b3020c032400eed60b649a2cbf55266e6bb0.tar.bz2 myconfigs-e573b3020c032400eed60b649a2cbf55266e6bb0.zip |
Add current configurations from old repository
Diffstat (limited to 'vim/bundle/vim-snippets/snippets/systemverilog.snippets')
-rw-r--r-- | vim/bundle/vim-snippets/snippets/systemverilog.snippets | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/vim/bundle/vim-snippets/snippets/systemverilog.snippets b/vim/bundle/vim-snippets/snippets/systemverilog.snippets new file mode 100644 index 0000000..70a9d2d --- /dev/null +++ b/vim/bundle/vim-snippets/snippets/systemverilog.snippets @@ -0,0 +1,73 @@ +extends verilog + +# Foreach Loop +snippet fe + foreach (${1}) begin + ${0} + end +# Do-while statement +snippet dowh + do begin + ${0} + end while (${1}); +# Combinational always block +snippet alc + always_comb begin ${1:: statement_label} + ${0} + end $1 +# Sequential logic +snippet alff + always_ff @(posedge ${1:clk}) begin ${2:: statement_label} + ${0} + end $2 +# Latched logic +snippet all + always_latch begin ${1:: statement_label} + ${0} + end $1 +# Class +snippet cl + class ${1:class_name}; + // data or class properties + ${0} + + // initialization + function new(); + endfunction : new + + endclass : $1 +# Typedef structure +snippet types + typedef struct { + ${0} + } ${1:name_t}; +# Program block +snippet prog + program ${1:program_name} (); + ${0} + endprogram : $1 +# Interface block +snippet intf + interface ${1:program_name} (); + // nets + ${0} + // clocking + + // modports + + endinterface : $1 +# Clocking Block +snippet clock + clocking ${1:clocking_name} @(${2:posedge} ${3:clk}); + ${0} + endclocking : $1 +# Covergroup construct +snippet cg + covergroup ${1:group_name} @(${2:posedge} ${3:clk}); + ${0} + endgroup : $1 +# Package declaration +snippet pkg + package ${1:package_name}; + ${0} + endpackage : $1 |