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authorPavel Pisa <pisa@cmp.felk.cvut.cz>2019-04-05 20:07:10 +0200
committerPavel Pisa <pisa@cmp.felk.cvut.cz>2019-04-05 20:07:10 +0200
commit299504df7e4882908e59fe7493fe133bf6271e8b (patch)
tree2bec45ffbbbaf252d0fbaa9a8889a97339f1a0fe
parent7becab88ae5287846299f22d291ccd44740fddbc (diff)
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qtmips_cli: add option to report number of required cycles and stalls.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
-rw-r--r--qtmips_cli/main.cpp3
-rw-r--r--qtmips_cli/reporter.cpp9
-rw-r--r--qtmips_cli/reporter.h2
-rw-r--r--qtmips_machine/core.cpp8
-rw-r--r--qtmips_machine/core.h3
5 files changed, 22 insertions, 3 deletions
diff --git a/qtmips_cli/main.cpp b/qtmips_cli/main.cpp
index e80670b..82296ed 100644
--- a/qtmips_cli/main.cpp
+++ b/qtmips_cli/main.cpp
@@ -65,6 +65,7 @@ void create_parser(QCommandLineParser &p) {
p.addOption({{"trace-hi", "tr-hi"}, "Print HI register changes."});
p.addOption({{"dump-registers", "d-regs"}, "Dump registers state at program exit."});
p.addOption({"dump-cache-stats", "Dump cache statistics at program exit."});
+ p.addOption({"dump-cycles", "Dump number of CPU cycles till program end."});
p.addOption({"dump-range", "Dump memory range.", "START,LENGTH,FNAME"});
p.addOption({"load-range", "Load memory range.", "START,FNAME"});
p.addOption({"expect-fail", "Expect that program causes CPU trap and fail if it doesn't."});
@@ -200,6 +201,8 @@ void configure_reporter(QCommandLineParser &p, Reporter &r, const SymbolTable *s
r.regs();
if (p.isSet("dump-cache-stats"))
r.cache_stats();
+ if (p.isSet("dump-cycles"))
+ r.cycles();
QStringList fail = p.values("fail-match");
for (int i = 0; i < fail.size(); i++) {
diff --git a/qtmips_cli/reporter.cpp b/qtmips_cli/reporter.cpp
index 74cbdc1..75d889b 100644
--- a/qtmips_cli/reporter.cpp
+++ b/qtmips_cli/reporter.cpp
@@ -53,6 +53,7 @@ Reporter::Reporter(QCoreApplication *app, QtMipsMachine *machine) : QObject() {
e_regs = false;
e_cache_stats = false;
+ e_cycles = false;
e_fail = (enum FailReason)0;
}
@@ -64,6 +65,10 @@ void Reporter::cache_stats() {
e_cache_stats = true;
}
+void Reporter::cycles() {
+ e_cycles = true;
+}
+
void Reporter::expect_fail(enum FailReason reason) {
e_fail = (enum FailReason)(e_fail | reason);
}
@@ -194,6 +199,10 @@ void Reporter::report() {
cout << "d-cache:stalled-cycles:" << machine->cache_data()->stalled_cycles() << endl;
cout << "d-cache:improved-speed:" << machine->cache_data()->speed_improvement() << endl;
}
+ if (e_cycles) {
+ cout << "cycles:" << machine->core()->cycles() << endl;
+ cout << "stalls:" << machine->core()->stalls() << endl;
+ }
foreach (DumpRange range, dump_ranges) {
ofstream out;
out.open(range.fname.toLocal8Bit().data(), ios::out | ios::trunc);
diff --git a/qtmips_cli/reporter.h b/qtmips_cli/reporter.h
index 5359908..bc223cb 100644
--- a/qtmips_cli/reporter.h
+++ b/qtmips_cli/reporter.h
@@ -49,6 +49,7 @@ public:
void regs(); // Report status of registers
void cache_stats();
+ void cycles();
enum FailReason {
FR_I = (1<<0), // Unsupported Instruction
@@ -78,6 +79,7 @@ private:
bool e_regs;
bool e_cache_stats;
+ bool e_cycles;
enum FailReason e_fail;
void report();
diff --git a/qtmips_machine/core.cpp b/qtmips_machine/core.cpp
index 88b2fe2..96ae0ad 100644
--- a/qtmips_machine/core.cpp
+++ b/qtmips_machine/core.cpp
@@ -72,10 +72,14 @@ void Core::reset() {
do_reset();
}
-unsigned Core::cycles() {
+unsigned Core::cycles() const {
return cycle_c;
}
+unsigned Core::stalls() const {
+ return stall_c;
+}
+
Registers *Core::get_regs() {
return regs;
}
@@ -935,7 +939,7 @@ bool StopExceptionHandler::handle_exception(Core *core, Registers *regs,
(unsigned long)regs->read_pc(), (unsigned long)mem_ref_addr);
#else
(void)excause; (void)inst_addr; (void)next_addr; (void)mem_ref_addr; (void)regs;
- (void)jump_branch_pc; (void)in_delay_slot;
+ (void)jump_branch_pc; (void)in_delay_slot, (void)core;
#endif
return true;
};
diff --git a/qtmips_machine/core.h b/qtmips_machine/core.h
index ff589c5..fd15315 100644
--- a/qtmips_machine/core.h
+++ b/qtmips_machine/core.h
@@ -76,7 +76,8 @@ public:
void step(bool skip_break = false); // Do single step
void reset(); // Reset core (only core, memory and registers has to be reseted separately)
- unsigned cycles(); // Returns number of executed cycles
+ unsigned cycles() const; // Returns number of executed cycles
+ unsigned stalls() const; // Returns number of stall cycles
Registers *get_regs();
Cop0State *get_cop0state();