From 789186fd63fb3fb63af1d8875cbe43609321b9d8 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Fri, 8 Feb 2019 13:52:59 +0100 Subject: Implement LL and SC as simple load and store word. SC returns 1 unconditionally. Signed-off-by: Pavel Pisa --- qtmips_machine/core.cpp | 17 +++++++++++++---- qtmips_machine/instruction.cpp | 6 ++++-- qtmips_machine/machinedefs.h | 2 ++ qtmips_machine/memory.cpp | 1 + 4 files changed, 20 insertions(+), 6 deletions(-) (limited to 'qtmips_machine') diff --git a/qtmips_machine/core.cpp b/qtmips_machine/core.cpp index 4164db0..2d33309 100644 --- a/qtmips_machine/core.cpp +++ b/qtmips_machine/core.cpp @@ -264,10 +264,19 @@ struct Core::dtMemory Core::memory(const struct dtExecute &dt) { } else { if (dt.memctl == AC_CACHE_OP) mem_data->sync(); - else if (memwrite) - mem_data->write_ctl(dt.memctl, mem_addr, dt.val_rt); - else if (memread) - towrite_val = mem_data->read_ctl(dt.memctl, mem_addr); + else if (memwrite) { + if (dt.memctl == AC_STORE_CONDITIONAL) { + mem_data->write_ctl(AC_WORD, mem_addr, dt.val_rt); + towrite_val = 1; + } else { + mem_data->write_ctl(dt.memctl, mem_addr, dt.val_rt); + } + } else if (memread) { + if (dt.memctl == AC_LOAD_LINKED) + towrite_val = mem_data->read_ctl(AC_WORD, mem_addr); + else + towrite_val = mem_data->read_ctl(dt.memctl, mem_addr); + } } emit memory_alu_value(dt.alu_val); diff --git a/qtmips_machine/instruction.cpp b/qtmips_machine/instruction.cpp index 393760c..d72dc7d 100644 --- a/qtmips_machine/instruction.cpp +++ b/qtmips_machine/instruction.cpp @@ -361,7 +361,8 @@ static const struct InstructionMap instruction_map[] = { .flags = IMF_MEM | IMF_MEM_STORE}, {"CACHE", IT_I, ALU_OP_ADDU, AC_CACHE_OP, nullptr, // CACHE .flags = IMF_SUPPORTED | IMF_ALUSRC | IMF_MEM| IMF_MEM_STORE}, - IM_UNKNOWN, // 48 + {"LL", IT_I, ALU_OP_ADDU, AC_LOAD_LINKED, nullptr, // LL + .flags = FLAGS_ALU_I_LOAD}, IM_UNKNOWN, // 49 IM_UNKNOWN, // 50 IM_UNKNOWN, // 51 @@ -369,7 +370,8 @@ static const struct InstructionMap instruction_map[] = { IM_UNKNOWN, // 53 IM_UNKNOWN, // 54 IM_UNKNOWN, // 55 - IM_UNKNOWN, // 56 + {"SC", IT_I, ALU_OP_ADDU, AC_STORE_CONDITIONAL, nullptr, // SW + .flags = FLAGS_ALU_I_STORE | IMF_MEMREAD | IMF_REGWRITE}, IM_UNKNOWN, // 57 IM_UNKNOWN, // 58 IM_UNKNOWN, // 59 diff --git a/qtmips_machine/machinedefs.h b/qtmips_machine/machinedefs.h index 2bf0556..5e8acd6 100644 --- a/qtmips_machine/machinedefs.h +++ b/qtmips_machine/machinedefs.h @@ -47,6 +47,8 @@ enum AccessControl { AC_WORD, AC_BYTE_UNSIGNED, AC_HALFWORD_UNSIGNED, + AC_LOAD_LINKED, + AC_STORE_CONDITIONAL, AC_CACHE_OP, }; diff --git a/qtmips_machine/memory.cpp b/qtmips_machine/memory.cpp index 79ac949..af9420b 100644 --- a/qtmips_machine/memory.cpp +++ b/qtmips_machine/memory.cpp @@ -123,6 +123,7 @@ std::uint32_t MemoryAccess::read_ctl(enum AccessControl ctl, std::uint32_t offse void MemoryAccess::sync() { } enum LocationStatus MemoryAccess::location_status(std::uint32_t address) const { + (void)address; return LOCSTAT_NONE; } -- cgit v1.2.3