From 179a1346a833d0039de5b0570f27045511b30dc4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Karel=20Ko=C4=8D=C3=AD?= <cynerd@email.cz>
Date: Sun, 8 Apr 2018 12:51:06 +0200
Subject: Implement sync for memory

---
 qtmips_machine/cache.cpp  |  4 ++++
 qtmips_machine/cache.h    |  3 ++-
 qtmips_machine/core.cpp   | 23 +++++++++++++++++++----
 qtmips_machine/core.h     | 23 +++++++++++++++--------
 qtmips_machine/memory.cpp |  2 ++
 qtmips_machine/memory.h   |  2 ++
 6 files changed, 44 insertions(+), 13 deletions(-)

(limited to 'qtmips_machine')

diff --git a/qtmips_machine/cache.cpp b/qtmips_machine/cache.cpp
index 7432119..d699cd6 100644
--- a/qtmips_machine/cache.cpp
+++ b/qtmips_machine/cache.cpp
@@ -69,6 +69,10 @@ void Cache::flush() {
                 kick(as, st);
 }
 
+void Cache::sync() {
+    flush();
+}
+
 unsigned Cache::hit() const {
     return hitc;
 }
diff --git a/qtmips_machine/cache.h b/qtmips_machine/cache.h
index 8fe7475..1882c6c 100644
--- a/qtmips_machine/cache.h
+++ b/qtmips_machine/cache.h
@@ -16,7 +16,8 @@ public:
     void wword(std::uint32_t address, std::uint32_t value);
     std::uint32_t rword(std::uint32_t address) const;
 
-    void flush(); // flush/sync cache
+    void flush(); // flush cache
+    void sync(); // Same as flush
 
     unsigned hit() const; // Number of recorded hits
     unsigned miss() const; // Number of recorded misses
diff --git a/qtmips_machine/core.cpp b/qtmips_machine/core.cpp
index 98b60e9..617f8c2 100644
--- a/qtmips_machine/core.cpp
+++ b/qtmips_machine/core.cpp
@@ -91,11 +91,26 @@ static const struct DecodeMap dmap[]  = {
 };
 
 Core::Core(Registers *regs, MemoryAccess *mem_program, MemoryAccess *mem_data) {
+    cycle_c = 0;
     this->regs = regs;
     this->mem_program = mem_program;
     this->mem_data = mem_data;
 }
 
+void Core::step() {
+    cycle_c++;
+    do_step();
+}
+
+void Core::reset() {
+    cycle_c = 0;
+    do_reset();
+}
+
+unsigned Core::cycles() {
+    return cycle_c;
+}
+
 struct Core::dtFetch Core::fetch() {
     Instruction inst(mem_program->read_word(regs->read_pc()));
     emit instruction_fetched(inst);
@@ -271,7 +286,7 @@ CoreSingle::~CoreSingle() {
         delete jmp_delay_decode;
 }
 
-void CoreSingle::step() {
+void CoreSingle::do_step() {
     struct dtFetch f = fetch();
     struct dtDecode d = decode(f);
     struct dtExecute e = execute(d);
@@ -284,7 +299,7 @@ void CoreSingle::step() {
         handle_pc(d);
 }
 
-void CoreSingle::reset() {
+void CoreSingle::do_reset() {
     if (jmp_delay_decode != nullptr)
         Core::dtDecodeInit(*jmp_delay_decode);
 }
@@ -295,7 +310,7 @@ CorePipelined::CorePipelined(Registers *regs, MemoryAccess *mem_program, MemoryA
     reset();
 }
 
-void CorePipelined::step() {
+void CorePipelined::do_step() {
     // Process stages
     writeback(dt_m);
     dt_m = memory(dt_e);
@@ -356,7 +371,7 @@ void CorePipelined::step() {
     }
 }
 
-void CorePipelined::reset() {
+void CorePipelined::do_reset() {
     dtFetchInit(dt_f);
     dtDecodeInit(dt_d);
     dtExecuteInit(dt_e);
diff --git a/qtmips_machine/core.h b/qtmips_machine/core.h
index 98f3e4a..3ea18ec 100644
--- a/qtmips_machine/core.h
+++ b/qtmips_machine/core.h
@@ -16,9 +16,10 @@ class Core : public QObject {
 public:
     Core(Registers *regs, MemoryAccess *mem_program, MemoryAccess *mem_data);
 
-    virtual void step() = 0; // Do single step
+    void step(); // Do single step
+    void reset(); // Reset core (only core, memory and registers has to be reseted separately)
 
-    virtual void reset() = 0; // Reset core (only core, memory and registers has to be reseted separately)
+    unsigned cycles(); // Returns number of executed cycles
 
 signals:
     void instruction_fetched(const machine::Instruction &inst);
@@ -29,6 +30,9 @@ signals:
     void instruction_program_counter(const machine::Instruction &inst);
 
 protected:
+    virtual void do_step() = 0;
+    virtual void do_reset() = 0;
+
     Registers *regs;
     MemoryAccess *mem_data, *mem_program;
 
@@ -76,6 +80,9 @@ protected:
     void dtDecodeInit(struct dtDecode &dt);
     void dtExecuteInit(struct dtExecute &dt);
     void dtMemoryInit(struct dtMemory &dt);
+
+private:
+    unsigned cycle_c;
 };
 
 class CoreSingle : public Core {
@@ -83,9 +90,9 @@ public:
     CoreSingle(Registers *regs, MemoryAccess *mem_program, MemoryAccess *mem_data, bool jmp_delay_slot);
     ~CoreSingle();
 
-    void step();
-
-    void reset();
+protected:
+    void do_step();
+    void do_reset();
 
 private:
     struct Core::dtDecode *jmp_delay_decode;
@@ -95,9 +102,9 @@ class CorePipelined : public Core {
 public:
     CorePipelined(Registers *regs, MemoryAccess *mem_program, MemoryAccess *mem_data, enum MachineConfig::HazardUnit hazard_unit = MachineConfig::HU_STALL_FORWARD);
 
-    void step();
-
-    void reset();
+protected:
+    void do_step();
+    void do_reset();
 
 private:
     struct Core::dtFetch dt_f;
diff --git a/qtmips_machine/memory.cpp b/qtmips_machine/memory.cpp
index f22c5f2..9ab7ef6 100644
--- a/qtmips_machine/memory.cpp
+++ b/qtmips_machine/memory.cpp
@@ -85,6 +85,8 @@ std::uint32_t MemoryAccess::read_ctl(enum MemoryAccess::AccessControl ctl, std::
     }
 }
 
+void MemoryAccess::sync() { }
+
 MemorySection::MemorySection(std::uint32_t length) {
     this->len = length;
     this->dt = new std::uint32_t[length];
diff --git a/qtmips_machine/memory.h b/qtmips_machine/memory.h
index 8dea63c..231cc34 100644
--- a/qtmips_machine/memory.h
+++ b/qtmips_machine/memory.h
@@ -31,6 +31,8 @@ public:
     void write_ctl(enum AccessControl ctl, std::uint32_t offset, std::uint32_t value);
     std::uint32_t read_ctl(enum AccessControl ctl, std::uint32_t offset) const;
 
+    virtual void sync();
+
 protected:
     virtual void wword(std::uint32_t offset, std::uint32_t value) = 0;
     virtual std::uint32_t rword(std::uint32_t offset) const = 0;
-- 
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