From 010194187d86041697f1e0e03edfc914940bd2ba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Karel=20Ko=C4=8D=C3=AD?= Date: Tue, 12 Dec 2017 21:18:45 +0100 Subject: Implement some store and load instructions --- qtmips_machine/tests/testcore.cpp | 116 +++++++++++++++++++++++++++++++++++- qtmips_machine/tests/testmemory.cpp | 58 ++++++++++++++++++ qtmips_machine/tests/tst_machine.h | 10 +++- 3 files changed, 180 insertions(+), 4 deletions(-) (limited to 'qtmips_machine/tests') diff --git a/qtmips_machine/tests/testcore.cpp b/qtmips_machine/tests/testcore.cpp index 593483a..c8f1a17 100644 --- a/qtmips_machine/tests/testcore.cpp +++ b/qtmips_machine/tests/testcore.cpp @@ -247,6 +247,7 @@ static void core_jmp_data() { << regs \ << 0x80000000 + (24 << 2); /* + * TODO QTest::newRow("JR") << Instruction(1, 15, 0, 61) \ << regs \ << regs.read_pc() + (24 << 2); @@ -305,10 +306,121 @@ void MachineTests::pipecore_jmp() { QCOMPARE(regs, regs_used); // There should be no change in registers now (except pc) } -void MachineTests::core_mem_data() { +static void core_mem_data() { + QTest::addColumn("i"); + QTest::addColumn("regs_init"); + QTest::addColumn("regs_res"); + QTest::addColumn("mem_init"); + QTest::addColumn("mem_res"); + + // Load + { + Memory mem; + mem.write_word(0x24, 0xA3242526); + Registers regs; + regs.write_gp(1, 0x22); + Registers regs_res(regs); + regs_res.write_gp(21, 0x80000023); + QTest::newRow("LB") << Instruction(32, 1, 21, 0x2) \ + << regs \ + << regs_res \ + << mem \ + << mem; + regs_res.write_gp(21, 0x80002324); + QTest::newRow("LH") << Instruction(33, 1, 21, 0x2) \ + << regs \ + << regs_res \ + << mem \ + << mem; + regs_res.write_gp(21, 0xA3242526); + QTest::newRow("LW") << Instruction(35, 1, 21, 0x2) \ + << regs \ + << regs_res \ + << mem \ + << mem; + regs_res.write_gp(21, 0x000000A3); + QTest::newRow("LBU") << Instruction(36, 1, 21, 0x2) \ + << regs \ + << regs_res \ + << mem \ + << mem; + regs_res.write_gp(21, 0x0000A324); + QTest::newRow("LHU") << Instruction(37, 1, 21, 0x2) \ + << regs \ + << regs_res \ + << mem \ + << mem; + } + // Store + { + Registers regs; + regs.write_gp(1, 0x22); + regs.write_gp(21, 0x23242526); + Memory mem; + mem.write_byte(0x24, 0x26); // Note: store least significant byte + QTest::newRow("SB") << Instruction(40, 1, 21, 0x2) \ + << regs \ + << regs \ + << Memory() \ + << mem; + mem.write_hword(0x24, 0x2526); + QTest::newRow("SH") << Instruction(41, 1, 21, 0x2) \ + << regs \ + << regs \ + << Memory() \ + << mem; + mem.write_word(0x24, 0x23242526); + QTest::newRow("SH") << Instruction(43, 1, 21, 0x2) \ + << regs \ + << regs \ + << Memory() \ + << mem; + } +} + +void MachineTests::singlecore_mem_data() { + core_mem_data(); +} + +void MachineTests::pipecore_mem_data() { + core_mem_data(); +} + +void MachineTests::singlecore_mem() { + QFETCH(Instruction, i); + QFETCH(Registers, regs_init); + QFETCH(Registers, regs_res); + QFETCH(Memory, mem_init); + QFETCH(Memory, mem_res); + + // Write instruction to both memories + mem_init.write_word(regs_init.read_pc(), i.data()); + mem_res.write_word(regs_init.read_pc(), i.data()); + CoreSingle core(®s_init, &mem_init); + core.step(); + + regs_res.pc_inc(); + QCOMPARE(regs_init, regs_res); + QCOMPARE(mem_init, mem_res); } -void MachineTests::core_mem() { +void MachineTests::pipecore_mem() { + QFETCH(Instruction, i); + QFETCH(Registers, regs_init); + QFETCH(Registers, regs_res); + QFETCH(Memory, mem_init); + QFETCH(Memory, mem_res); + + // Write instruction to both memories + mem_init.write_word(regs_init.read_pc(), i.data()); + mem_res.write_word(regs_init.read_pc(), i.data()); + + CorePipelined core(®s_init, &mem_init); + for (int i = 0; i < 5; i++) + core.step(); // Fire steps for five pipelines stages + regs_res.pc_jmp(20); + QCOMPARE(regs_init, regs_res); + QCOMPARE(mem_init, mem_res); } diff --git a/qtmips_machine/tests/testmemory.cpp b/qtmips_machine/tests/testmemory.cpp index 091c26d..f1c6b80 100644 --- a/qtmips_machine/tests/testmemory.cpp +++ b/qtmips_machine/tests/testmemory.cpp @@ -103,3 +103,61 @@ void MachineTests::memory_compare() { m3.write_byte(0x18, 0x22); QVERIFY(m1 != m3); } + +void MachineTests::memory_write_ctl_data() { + QTest::addColumn("ctl"); + QTest::addColumn("result"); + + Memory mem; + QTest::newRow("none") << MemoryAccess::AC_NONE \ + << mem; + mem.write_byte(0x20, 0x26); + QTest::newRow("byte") << MemoryAccess::AC_BYTE \ + << mem; + QTest::newRow("byte-unsigned") << MemoryAccess::AC_BYTE_UNSIGNED \ + << mem; + mem.write_hword(0x20, 0x2526); + QTest::newRow("halfword") << MemoryAccess::AC_HALFWORD \ + << mem; + QTest::newRow("haldword-unsigned") << MemoryAccess::AC_HALFWORD_UNSIGNED \ + << mem; + mem.write_word(0x20, 0x23242526); + QTest::newRow("word") << MemoryAccess::AC_WORD \ + << mem; +} + +void MachineTests::memory_write_ctl() { + QFETCH(MemoryAccess::AccessControl, ctl); + QFETCH(Memory, result); + + Memory mem; + mem.write_ctl(ctl, 0x20, 0x23242526); + QCOMPARE(mem, result); +} + +void MachineTests::memory_read_ctl_data() { + QTest::addColumn("ctl"); + QTest::addColumn("result"); + + QTest::newRow("none") << MemoryAccess::AC_NONE \ + << (std::uint32_t)0; + QTest::newRow("byte") << MemoryAccess::AC_BYTE \ + << (std::uint32_t)0x80000023; + QTest::newRow("halfword") << MemoryAccess::AC_HALFWORD \ + << (std::uint32_t)0x80002324; + QTest::newRow("word") << MemoryAccess::AC_WORD \ + << (std::uint32_t)0xA3242526; + QTest::newRow("byte-unsigned") << MemoryAccess::AC_BYTE_UNSIGNED \ + << (std::uint32_t)0xA3; + QTest::newRow("halfword-unsigned") << MemoryAccess::AC_HALFWORD_UNSIGNED \ + << (std::uint32_t)0xA324; +} + +void MachineTests::memory_read_ctl() { + QFETCH(MemoryAccess::AccessControl, ctl); + QFETCH(std::uint32_t, result); + + Memory mem; + mem.write_word(0x20, 0xA3242526); + QCOMPARE(mem.read_ctl(ctl, 0x20), result); +} diff --git a/qtmips_machine/tests/tst_machine.h b/qtmips_machine/tests/tst_machine.h index 9b33e68..ad3112c 100644 --- a/qtmips_machine/tests/tst_machine.h +++ b/qtmips_machine/tests/tst_machine.h @@ -19,6 +19,10 @@ private Q_SLOTS: void memory_section_data(); void memory_endian(); void memory_compare(); + void memory_write_ctl(); + void memory_write_ctl_data(); + void memory_read_ctl(); + void memory_read_ctl_data(); // Program loader void program_loader(); // Instruction @@ -38,8 +42,10 @@ private Q_SLOTS: void singlecore_jmp_data(); void pipecore_jmp(); void pipecore_jmp_data(); - void core_mem(); - void core_mem_data(); + void singlecore_mem(); + void singlecore_mem_data(); + void pipecore_mem(); + void pipecore_mem_data(); }; #endif // TST_MACHINE_H -- cgit v1.2.3