From 73886d9d1733368fe3c876c8e613ba5821e12944 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Mon, 4 Mar 2019 22:38:34 +0100 Subject: Use irq 3 (HW1) for Rx and irq 2 (HW0) for Tx to be compatible with SPIM. Jump to address 0x8000180 by default and to EBase + 0x180 when EBase is set to be compatible with real MIPS CPU. Signed-off-by: Pavel Pisa --- qtmips_machine/machinedefs.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'qtmips_machine/machinedefs.h') diff --git a/qtmips_machine/machinedefs.h b/qtmips_machine/machinedefs.h index eb7f6d4..8ccc81c 100644 --- a/qtmips_machine/machinedefs.h +++ b/qtmips_machine/machinedefs.h @@ -58,8 +58,12 @@ enum AccessControl { }; enum ExceptionCause { - EXCAUSE_NONE = 0, - EXCAUSE_INT = 1, + EXCAUSE_NONE = 0, // Use zero as default value when no exception is pending + EXCAUSE_INT = 1, // Int is 0 on real CPU and in Cause regsiter + EXCAUSE_ADDRL = 4, + EXCAUSE_ADDRS = 5, + EXCAUSE_IBUS = 6, + EXCAUSE_DBUS = 7, EXCAUSE_SYSCALL = 8, EXCAUSE_BREAK = 9, EXCAUSE_OVERFLOW = 12, -- cgit v1.2.3