From adb9f147e358f687b37f5bf14c68f559c7c86a79 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Wed, 20 Feb 2019 14:17:32 +0100 Subject: Distinguish between write-through cache with allocate and update only if hit. Add into cache statistic number of backing/main memory accesses. Correction of meaning and computation of the cache statistic. Signed-off-by: Pavel Pisa --- qtmips_machine/machineconfig.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'qtmips_machine/machineconfig.cpp') diff --git a/qtmips_machine/machineconfig.cpp b/qtmips_machine/machineconfig.cpp index 9cd6465..8a48ce1 100644 --- a/qtmips_machine/machineconfig.cpp +++ b/qtmips_machine/machineconfig.cpp @@ -54,7 +54,7 @@ using namespace machine; #define DFC_BLOCKS 1 #define DFC_ASSOC 1 #define DFC_REPLAC RP_RAND -#define DFC_WRITE WP_TROUGH +#define DFC_WRITE WP_TROUGH_NOALLOC ////////////////////////////////////////////////////////////////////////////// MachineConfigCache::MachineConfigCache() { @@ -106,7 +106,7 @@ void MachineConfigCache::preset(enum ConfigPresets p) { set_blocks(2); set_associativity(2); set_replacement_policy(RP_RAND); - set_write_policy(WP_TROUGH); + set_write_policy(WP_TROUGH_NOALLOC); break; case CP_SINGLE: case CP_PIPE_NO_HAZARD: -- cgit v1.2.3